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Table of Contents
Demonstration of Haze Reduction image processing H/W IP on SoC FPGA
Demonstration of Haze Reduction image processing H/W IP on SoC FPGA
27 June 2015 - 01:46
|
Version 62
|
Chris Martin
| Demo | CV SoC, Cyclone V, Cyclone V SoC, DVI, Demo, Helio
| Board: | MacnicaHelioSoCEvaluationKit |
|---|---|
| Tools Version: | 13.1 |
| State: | running |
| Members: | NSWipDesign, YuSaito |
| Homepage: | http://www.nsw.co.jp/solution/lsi-e/english/hazereduction/e_FPGA.html |
Video
403 Forbidden
Haze Reduction Hardware IP
Haze Reduction is IP module that reduces to damp haze or fog in images; it can improve the visibility and readability by digital image processing. High-Speed frame rate video is processed enhancement in real time by hardware implementation.We implement the algorithm of image sharpening to the hardware, and it makes the input full hi-vision, even bigger size image sharp. How much size it can be processed is depended on the implementation size of line buffer and the operation speed of the hardware. For example, it’s able to show you the processed image of full frame rate with Full hi-vision size at FPGA implementation. All processing functions of Haze Reduction IP are implemented into hardware, but it needs input and output video stream interface and setting parameters. Therefore it will be possible to configure fully hardware, but the embedded processor control parameters will be more flexible and useful.
System configuration
Haze Reduction IP processes video signal in real time. This IP is not only used for the dedicated hardware equipment, but also is used as configured processing module in video processing system. The video processing systems usually incorporate embedded microprocessor and video DSP with specific function based processing hardware modules. In this demonstration system is using ALTERA Cyclone V SoC FPGA device. The System is running Linux and controlling video stream data between input port, main memory and output port. And the application is handling processing parameters of Haze Reduction. Haze Reduction IP built in FPGA part with other IO interface and bus bridge modules. See below the block diagram.The demo system performance target
| Specification | Value |
| Video Size | 1024(H) x 768(V) Note:Haze Reduction IP supports Full HD |
| Frame rate | 60 frame per second (Real time processing speed) |
| Color format | RGB, 24bit per pixel |
Demonstration
Connections
Block diagram
Haze Reduction IP is implemented into Helio sample design.
Development environment
| FPGA Tool | Quartus II : Version 13.1 Update 4 Nios II : Version 13.1 Update 4 |
| Hardware | Macnica Cyclone V SoC Starter Kit (Helio) (FPGA : 5CSXFC6C6U23ES) Bitec HSMC DVI Daughter Board |
| Software (OS) | Linux for Helio board |
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