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GSRD for Agilex 7 F-Series Transceiver-SoC DevKit (P-Tile and E-Tile)
Golden System Reference Design for DK-SI-AGF014EA

23 January 2024 - 16:07 | Release 23.4 | RolandoSantoyo | Agilex, DK-SI-AGF014EA, DK-SI-AGF014EB, GHRD, GSRD, Golden System Reference Design, Linux, SoC, U-Boot, Yocto, fm61

Overview
Running GSRD with Pre-Built Binaries for the DK-SI-AGF014EA Version
Building the GSRD for the DK-SI-AGF014EA Version
Booting from QSPI for the DK-SI-AGF014EA Version
Booting From NAND for the DK-SI-AGF014EA Version
Partial Reconfiguration for the DK-SI-AGF014EA Version
Building the GSRD for the DK-SI-AGF014EB Version
Disabling Unused Flash Devices in U-Boot for Faster Booting
Reconfiguring Core Fabric from U-Boot

Overview

Prerequisites

The following are required in order to be able to fully exercise the Agilex GSRD:

Intel Agilex® 7 FPGA F-Series Transceiver-SoC Development Kit (Production 1 P-Tiles & E-Tiles) ordering code DK-SI-AGF014EA or DK-SI-AGF014EB (SD card boot only)
- SD/MMC HPS Daughtercard
- SDM QSPI Bootcard
- Mini USB cable for serial output
- Micro USB cable for on-board Intel FPGA Download Cable II
Micro SD card (4GB or greater)
Host PC with
- Linux - Ubuntu 22.04LTS was used to create this page, other versions and distributions may work too
- Serial terminal (for example Minicom on Linux and TeraTerm or PuTTY on Windows)
- Micro SD card slot or Micro SD card writer/reader
- Intel Quartus Prime Pro Edition
  - v23.3 was used for binary release
  - v23.4 used for rebuilding
Local Ethernet network, with DHCP server (will be used to provide IP address to the board)

You can determine your board version by referring to the following table from https://www.intel.com/content/www/us/en/docs/programmable/683752/current/overview.html

Development Kit Version	Ordering Code	Device Part Number	Starting Serial Number
Intel Agilex® 7 FPGA F-Series Transceiver-SoC Development Kit (Production 2 P-Tiles & E-Tiles)	DK-SI-AGF014EB	AGFB014R24B2E2V (Power Solution 2)	00205001
Intel Agilex® 7 FPGA F-Series Transceiver-SoC Development Kit (Production 1 P-Tiles & E-Tiles)	DK-SI-AGF014EA	AGFB014R24B2E2V (Power Solution 1)	0001101
Intel Agilex® 7 FPGA F-Series Transceiver-SoC Development Kit (ES P-Tiles & E-Tiles)	DK-SI-AGF014E3ES	AGFB014E3ES (Power Solution 1)	0001001

For the DK-SI-AGF014EA version the following are provided:

Prebuilt binaries for SD Card boot, QSPI boot, NAND boot and Partial Reconfiguration
Instructions how to rebuild the binaries for SD Card boot, QSPI boot, NAND boot and Partial Reconfiguration
Instructions on how to exercise SD Card boot, QSPI boot, NAND boot and Partial Reconfiguration

For the DK-SI-AGF014EB version the following are provided:

Prebuilt binaries for SD Card boot,
Instructions on how to build the binaries for SD card boot

The DK-SI-AGF014EB version of the board differs from the DK-SI-AGF014EA version in that it uses Linear power regulators instead of Enpirion. Apart from this, the functionality is the same for both versions of the board. Refer to Building the GSRD for the DK-SI-45AGF014EB Version for details on how to update the hardware design and build the binaries fore the DK-SI-AGF014EB version.

The U-Boot and Linux compilation, Yocto compilation and creating the SD card image require a Linux host PC. The rest of the operations can be performed on either a Windows or Linux host PC.

Release Contents

Intel FPGA HPS Embedded Software Release Notes

The Intel FPGA HPS Embedded Software release notes can be accessed from the following link: https://www.rocketboards.org/foswiki/Documentation/IntelFPGAHPSEmbeddedSoftwareRelease

Latest Binaries Release Content

Boot from SD Card Binaries

The release files are accessible at

For DK-SI-AGF014EA: https://releases.rocketboards.org/2023.09/gsrd/agilex7_dk_si_agf014ea_gsrd/
For DK-SI-AGF014EB : https://releases.rocketboards.org/2023.09/gsrd/agilex7_dk_si_agf014eb_gsrd/

The source code is also included on the SD card in the Linux rootfs path /home/root:

File	Description
linux-socfpga-v6.1.38-lts-src.tar.gz	Source code for Linux kernel
u-boot-socfpga-v2023.04-src.tar.gz	Source code for U-Boot
arm-trusted-firmware-v2.9.0-src.tar.gz	Source code for Arm Trusted Firmware

Before downloading the hardware design please read the agreement in the link https://www.intel.com/content/www/us/en/programmable/downloads/software/license/lic-prog_lic.html

Boot from NAND Binaries

The release files are accessible at https://releases.rocketboards.org/2023.09/nand/agilex7_dk_si_agf014ea_nand/.

To load the binaries in the development kit see Write NAND Binaries.

Boot from QSPI Binaries

The release files are accessible at https://releases.rocketboards.org/2023.09/qspi/agilex7_dk_si_agf014ea_qspi/.

Latest Source Code Release Contents - Branches and Commit IDs

Quartus Prime Pro v23.4 and the following software component versions are used to build the GSRD:

Component	Location	Branch	Commit ID/Tag
GHRD	https://github.com/altera-opensource/ghrd-socfpga	master	QPDS23.4_REL_GSRD_PR
Linux	https://github.com/altera-opensource/linux-socfpga	socfpga-6.1.55-lts	QPDS23.4_REL_GSRD_PR
Arm Trusted Firmware	https://github.com/arm-trusted-firmware	socfpga_v2.9.1	QPDS23.4_REL_GSRD_PR
U-Boot	https://github.com/altera-opensource/u-boot-socfpga	socfpga_v2023.07	QPDS23.4_REL_GSRD_PR
Yocto Project	https://git.yoctoproject.org/poky	nanbield	latest
Yocto Project: meta-intel-fpga	https://git.yoctoproject.org/meta-intel-fpga	nanbield	latest
Yocto Project: meta-intel-fpga-refdes	https://github.com/altera-opensource/meta-intel-fpga-refdes	nanbield	QPDS23.4_REL_GSRD_PR

GHRD Overview

The Golden Hardware Reference Design is an important part of the GSRD and consists of the following components:

Hard Processor System (HPS)
- Quad Arm Cortex-A53 MPCore Processor
- HPS Peripherals connected to Out-of-Box Experience (OOBE) Daughter Card:
  - Micro SD for HPS storage
  - EMAC
  - HPS JTAG debug
  - I2C
  - USB UART
  - USB 2.0 OTG
  - Two Push buttons and Three LEDs
Hard Memory Controller (HMC) for HPS External Memory Interface (EMIF)
FPGA Peripherals connected to Lightweight HPS-to-FPGA (LWH2F) AXI Bridge and JTAG to Avalon Master Bridge
- Three user LED outputs
- Four user DIP switch inputs
- Four user push-button inputs
- Interrupt Latency Counter
- System ID
FPGA Peripherals connected to HPS-to-FPGA (H2F) AXI Bridge
- 256KB of FPGA on-chip memory
JTAG to Avalon Master Bridges connected to:
- FPGA-to-SDRAM 0/1/2 Interfaces
- FPGA-to-HPS AXI Bridge

The GHRD allows hardware designers to access each peripheral in the FPGA portion of the SoC with System Console, through the JTAG master module. This signal-level access is independent of the driver readiness of each peripheral.

Cortex-A53 MPU Address Maps

This section presents the address maps as seen from the MPU (Cortex-A53) side.

HPS-to-FPGA Address Map

The MPU region provide windows of 4 GB into the FPGA slave address space. The lower 1.5 GB of this space is mapped to two separate addresses - firstly from 0x8000_0000 to 0xDFFF_FFFF and secondly from 0x20_0000_0000 to 0x20_5FFF_FFFF. The following table lists the offset of each peripheral from the HPS-to-FPGA bridge in the FPGA portion of the SoC.

Peripheral	Address Offset	Size (bytes)	Attribute
onchip_memory2_0	0x0	256K	On-chip RAM as scratch pad

Lightweight HPS-to-FPGA Address Map

The the memory map of system peripherals in the FPGA portion of the SoC as viewed by the MPU (Cortex-A53), which starts at the lightweight HPS-to-FPGA base address of 0xF900_0000, is listed in the following table.

Peripheral	Address Offset	Size (bytes)	Attribute
sysid	0x0000_0000	8	Unique system ID
led_pio	0x0000_1080	16	LED outputs
button_pio	0x0000_1060	16	Push button inputs
dipsw_pio	0x0000_1070	16	DIP switch inputs
ILC	0x0000_1100	256	Interrupt latency counter (ILC)

JTAG Master Address Map

There are two JTAG master interfaces in the design, one for accessing non-secure peripherals in the FPGA fabric, and another for accessing secure peripheral in the HPS through the FPGA-to-HPS Interface.

The following table lists the address of each peripheral in the FPGA portion of the SoC, as seen through the non-secure JTAG master interface.

Peripheral	Address Offset	Size (bytes)	Attribute
onchip_memory2_0	0x0000_0000	256K	On-chip RAM
sysid	0x0004_0000	8	Unique system ID
led_pio	0x0004_0080	16	LED outputs
button_pio	0x0004_0060	16	Push button inputs
dipsw_pio	0x0004_0070	16	DIP switch inputs
ILC	0x0004_0100	256	Interrupt latency counter (ILC)

Interrupt Routing

The HPS exposes 64 interrupt inputs for the FPGA logic. The following table lists the interrupt connections from soft IP peripherals to the HPS interrupt input interface.

Peripheral	Interrupt Number	Attribute
dipsw_pio	f2h_irq0[0]	4 DIP switch inputs
button_pio	f2h_irq0[1]	4 Push button inputs

The interrupt sources are also connected to an interrupt latency counter (ILC) module in the system, which enables System Console to be aware of the interrupt status of each peripheral in the FPGA portion of the SoC.

Typical HPS Boot Flow

The GSRD boot flow includes the following stages:

SDM
U-Boot SPL
ATF
U-Boot
Linux
Application

The following table presents a short description of the different boot stages:

Stage	Description
SDM	Secure Device Manager boots first
U-Boot SPL	Configures IO, FPGA, brings up SDRAM
ATF	Arm Trusted Firmware, provides SMC handler
U-Boot	Loads Linux kernel
Linux	Operating system
Application	User application

For more information, please refer to Intel Agilex Hard Processor System Technical Reference Manual (Booting and Configuration chapter).

Running GSRD with Pre-Built Binaries for the DK-SI-AGF014EA Version

Booting Linux Using Precompiled Binaries

This section presents how to write the QSPI Falsh and SD Card image files, configure the board and boot Linux.

Configuring Board

This section presents the necessary board settings in order to run the GSRD on the Intel Agilex SoC development board.

First, confirm the following:

SD Card/OOBE Daughter card is installed on HPS Daughter card socket

Then the board switches need to be configured as follows:

SW1: ON-OFF-OFF-ON
SW2: all OFF
SW3: OFF-OFF-ON-ON-ON-ON
SW4: OFF-OFF-OFF-ON
SW5: all OFF
SW6: OFF-OFF-OFF-ON
SW9: OFF-OFF
SW10: OFF-ON

Writing JIC Image to QSPI Flash

The QSPI JIC image contains the FPGA configuration bitstream, and the U-Boot SPL.

1. Download and extract the image file:

For DK-SI-AGF014EA:

cd $TOP_FOLDER
wget https://releases.rocketboards.org/2023.09/gsrd/agilex7_dk_si_agf014ea_gsrd/ghrd_agfb014r24b2e2v.jic.tar.gz
tar xf ghrd_agfb014r24b2e2v.jic.tar.gz

For DK-SI-AGF014EB:

cd $TOP_FOLDER
wget https://releases.rocketboards.org/2023.09/gsrd/agilex7_dk_si_agf014eb_gsrd/ghrd_agfb014r24b2e2v.jic.tar.gz
tar xf ghrd_agfb014r24b2e2v.jic.tar.gz

2. Configure MSEL to JTAG:

SW1: ON-ON-ON-ON

3. Power cycle the board

4. Write the image using the following commands:

cd $TOP_FOLDER
~/intelFPGA_pro/23.4/nios2eds/nios2_command_shell.sh \
quartus_pgm -c 1 -m jtag -o "pvi;ghrd_agfb014r24b2e2v.jic"

5. Configure MSEL back to QSPI:

SW1: ON-OFF-OFF-ON

Creating SD Card

This section explains how to create the SD card necessary to boot Linux, using the SD card image available with the pre-built Linux binaries package. Once the SD card has been created, insert the card into the SD slot of the Micro SD daughter card.

Creating SD Card on Linux

1. Download the SD card image and extract it:

For DK-SI-AGF014EA:

wget https://releases.rocketboards.org/2023.09/gsrd/agilex7_dk_si_agf014ea_gsrd/sdimage.tar.gz
tar xf sdimage.tar.gz

For DK-SI-AGF014EB:

wget https://releases.rocketboards.org/2023.09/gsrd/agilex7_dk_si_agf014ea_gsrd/sdimage.tar.gz
tar xf sdimage.tar.gz

The extacted file is named gsrd-console-image-agilex7.wic.

2. Determine the device associated with the SD card on the host by running the following command before and after inserting the card.

$ cat /proc/partitions

Let's assume it is /dev/sdx.

3. Use dd utility to write the SD image to the SD card.

$ sudo dd if=gsrd-console-image-agilex7.wic of=/dev/sdx bs=1M

Note we are using sudo to be able to write to the card.

4. Use sync utility to flush the changes to the SD card.

$ sudo sync

Creating SD Card on Windows

1. Download the SD card image and extract it:

For DK-SI-AGF014EA:

wget https://releases.rocketboards.org/2023.09/gsrd/agilex7_dk_si_agf014ea_gsrd/sdimage.tar.gz

For DK-SI-AGF014EB:

wget https://releases.rocketboards.org/2023.09/gsrd/agilex7_dk_si_agf014ea_gsrd/sdimage.tar.gz

The extacted file is named gsrd-console-image-agilex7.wic.

2. Rename the wic file as sdcard.img

3. Use Win32DiskImager to write the image to the SD card. The tool can be downloaded from https://sourceforge.net/projects/win32diskimager/files/latest/download

Configuring Serial Connection

The OOBE Daughter Card has a built-in FTDI USB to Serial converter chip that allows the host computer to see the board as a virtual serial port. Ubuntu and other modern Linux distributions have built-in drivers for the FTDI USB to Serial converter chip, so no driver installation is necessary on those platforms. On Windows, the SoC EDS Pro installer automatically installs the required drivers if necessary.

The serial communication parameters are:

Baud-rate: 115,200
Parity: none
Flow control: none
Stop bits: 1

On Windows, utilities such as TeraTerm and PuTTY can be used to connect to the board. They are easily configured from the tool menus.

On Linux, the minicom utility can be used. Here is how to configure it:

1. The virtual serial port is usually named /dev/ttyUSB0. In order to determine the device name associated with the virtual serial port on your host PC, please perform the following:

Use the following command to determine which USB serial devices are already installed: ls /dev/ttyUSB*
Connect mini USB cable from J7 to the PC. This will enable the PC to communicate with the board, even if the board is not powered yet.
Use the ls /dev/ttyUSB* command command again to determine which new USB serial device appeared.

2. Install minicom application on host PC, if not installed.

On Ubuntu, use sudo apt-get install minicom

3. Configure minicom.

$ sudo minicom -s

Under Serial Port Setup choose the following:

Serial Device: /dev/ttyUSB0 (edit to match the system as necessary)
Bps/Par/Bits: 115200 8N1
Hardware Flow Control: No
Software Flow Control: No
Hit [ESC] to return to the main configuration menu

Select Save Setup as dfl to save the default setup. Then select Exit.

Booting Linux

This section presents how to boot Linux on the board. The required steps are:

1. Start serial terminal (when using Minicom it will connect using the selected settings, for others connect manually).

2. Power up the board.

3. U-Boot SPL is ran

4. U-Boot is ran

5. Linux boots.

6. Login using 'root' and no password.

U-Boot SPL 2023.04 (Oct 03 2023 - 08:37:14 +0000)
Reset state: Cold
MPU          1200000 kHz
L4 Main        400000 kHz
L4 sys free   100000 kHz
L4 MP         200000 kHz
L4 SP         100000 kHz
SDMMC          50000 kHz
DDR: 8192 MiB
SDRAM-ECC: Initialized success with 1738 ms
QSPI: Reference clock at 400000 kHz
WDT:   Started watchdog@ffd00200 with servicing every 1000ms (10s timeout)
denali-nand-dt nand@ffb90000: timeout while waiting for irq 0x2000
denali-nand-dt nand@ffb90000: reset not completed.
Trying to boot from MMC1
## Checking hash(es) for config board-4 … OK
## Checking hash(es) for Image atf … crc32+ OK
## Checking hash(es) for Image uboot … crc32+ OK
## Checking hash(es) for Image fdt-0 … crc32+ OK
NOTICE:  BL31: v2.9.0(release):QPDS23.4_REL_GSRD_PR
NOTICE:  BL31: Built : 06:03:01, Oct 13 2023

U-Boot 2023.04 (Oct 03 2023 - 08:37:14 +0000)socfpga_agilex

CPU:   Intel FPGA SoCFPGA Platform (ARMv8 64bit Cortex-A53)
Model: SoCFPGA Agilex SoCDK
DRAM:  2 GiB (effective 8 GiB)
Core:  29 devices, 24 uclasses, devicetree: separate
WDT:   Started watchdog@ffd00200 with servicing every 1000ms (10s timeout)
NAND:  denali-nand-dt nand@ffb90000: timeout while waiting for irq 0x2000
denali-nand-dt nand@ffb90000: reset not completed.
Failed to initialize Denali NAND controller. (error -5)
0 MiB
MMC:   dwmmc0@ff808000: 0
Loading Environment from FAT... Unable to read "uboot.env" from mmc0:1...
Loading Environment from UBI... denali-nand-dt nand@ffb90000: timeout while waiting for irq 0x2000
denali-nand-dt nand@ffb90000: reset not completed.
SF: Detected mt25qu02g with page size 256 Bytes, erase size 64 KiB, total 256 MiB
Could not find a valid device for ffb90000.nand.0
Volume env not found!

** Unable to read env from root:env **
In:    serial0@ffc02000
Out:   serial0@ffc02000
Err:   serial0@ffc02000
Net:   
Warning: ethernet@ff800000 (eth0) using random MAC address - ca:21:22:c5:09:ed
eth0: ethernet@ff800000
Hit any key to stop autoboot:  0 
switch to partitions #0, OK
mmc0 is current device
Scanning mmc 0:1...
Found U-Boot script /boot.scr.uimg
2403 bytes read in 3 ms (782.2 KiB/s)
## Executing script at 05ff0000
crc32+ Trying to boot Linux from device mmc0
Found kernel in mmc0
16141779 bytes read in 727 ms (21.2 MiB/s)
## Loading kernel from FIT Image at 02000000 …
   Using 'board-4' configuration
   Verifying Hash Integrity … OK
   Trying 'kernel' kernel subimage
     Description:  Linux Kernel
     Type:         Kernel Image
     Compression:  lzma compressed
     Data Start:   0x020000dc
     Data Size:    9250506 Bytes = 8.8 MiB
     Architecture: AArch64
     OS:           Linux
     Load Address: 0x06000000
     Entry Point:  0x06000000
     Hash algo:    crc32
     Hash value:   ac6dd851
   Verifying Hash Integrity … crc32+ OK
## Loading fdt from FIT Image at 02000000 …
   Using 'board-4' configuration
   Verifying Hash Integrity … OK
   Trying 'fdt-4' fdt subimage
     Description:  socfpga_socdk_combined
     Type:         Flat Device Tree
     Compression:  uncompressed
     Data Start:   0x028ea0bc
     Data Size:    33653 Bytes = 32.9 KiB
     Architecture: AArch64
     Hash algo:    crc32
     Hash value:   6fa0865c
   Verifying Hash Integrity … crc32+ OK
   Booting using the fdt blob at 0x28ea0bc
Working FDT set to 28ea0bc
## Loading fpga from FIT Image at 02000000 …
   Trying 'fpga-4' fpga subimage
     Description:  FPGA bitstream for GHRD
     Type:         FPGA Image
     Compression:  uncompressed
     Data Start:   0x02d29664
     Data Size:    2338816 Bytes = 2.2 MiB
     Load Address: 0x0a000000
     Hash algo:    crc32
     Hash value:   881f6855
   Verifying Hash Integrity … crc32+ OK
   Loading fpga from 0x02d29664 to 0x0a000000
…FPGA reconfiguration OK!
Enable FPGA bridges
   Programming full bitstream... OK
   Uncompressing Kernel Image
   Loading Device Tree to 000000007ead5000, end 000000007eae0374 … OK
Working FDT set to 7ead5000
Removing MTD device #2 (root) with use count 1
Error when deleting partition "root" (-16)
SF: Detected mt25qu02g with page size 256 Bytes, erase size 64 KiB, total 256 MiB
Enabling QSPI at Linux DTB...
Working FDT set to 7ead5000
libfdt fdt_path_offset() returned FDT_ERR_NOTFOUND
libfdt fdt_path_offset() returned FDT_ERR_NOTFOUND
QSPI clock frequency updated
RSU: Firmware or flash content not supporting RSU
RSU: Firmware or flash content not supporting RSU
RSU: Firmware or flash content not supporting RSU
RSU: Firmware or flash content not supporting RSU

Starting kernel …

Deasserting all peripheral resets
[    0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034]
[    0.000000] Linux version 6.1.38-altera (oe-user@oe-host) (aarch64-poky-linux-gcc (GCC) 12.3.0, GNU ld (GNU Binutils) 2.40.0.20230703) #1 SMP PREEMPT Mon Oct  2 06:02:34 UTC 2023
[    0.000000] Machine model: SoCFPGA Agilex SoCDK

…

[     7.129984] socfpga-dwmac ff800000.ethernet eth0: Link is Up - 1Gbps/Full - flow control off
[     7.138511] IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready
[     7.170769] 8021q: 802.1Q VLAN Support v1.8

Poky (Yocto Project Reference Distro) 4.2.3 agilex7dksiagf014ea ttyS0

agilex7dksiagf014ea login: root
root@agilex7dksiagf014ea:~#

7. Run 'ifconfig' command to determine the IP of the board

root@agilex7dksiagf014ea:~# ifconfig
eth0: flags=4163  mtu 1500
        inet 192.168.1.163  netmask 255.255.255.0  broadcast 192.168.1.255
        inet6 fe80::20cd:5eff:fe36:dbaf  prefixlen 64  scopeid 0x20
        ether 22:cd:5e:36:db:af  txqueuelen 1000  (Ethernet)
        RX packets 14  bytes 2126 (2.0 KiB)
        RX errors 0  dropped 0  overruns 0  frame 0
        TX packets 43  bytes 7513 (7.3 KiB)
        TX errors 0  dropped 0 overruns 0  carrier 0  collisions 0
        device interrupt 21  base 0x2000  

eth1: flags=4099  mtu 1500
        ether 5a:4d:ca:de:cd:f6  txqueuelen 1000  (Ethernet)
        RX packets 0  bytes 0 (0.0 B)
        RX errors 0  dropped 0  overruns 0  frame 0
        TX packets 0  bytes 0 (0.0 B)
        TX errors 0  dropped 0 overruns 0  carrier 0  collisions 0
        device interrupt 22  base 0xc000  

lo: flags=73  mtu 65536
        inet 127.0.0.1  netmask 255.0.0.0
        inet6 ::1  prefixlen 128  scopeid 0x10
        loop  txqueuelen 1000  (Local Loopback)
        RX packets 100  bytes 8468 (8.2 KiB)
        RX errors 0  dropped 0  overruns 0  frame 0
        TX packets 100  bytes 8468 (8.2 KiB)
        TX errors 0  dropped 0 overruns 0  carrier 0  collisions 0

Note: there are two IP addresses, one coming from the Ethernet port on the HPS Daughtercard, and one from the Ethernet port on the DevKit, which is connected throgh SGMII.

Running Sample Linux Applications

The GSRD includes a number of sample Linux applications that help demonstrate some of the features of the platform:

Display Hello World message
Control LEDs
Detect interrupts from push buttons and DIP switches

The sample applications can be used as a starting point for users to write their own applications that interact with software IP through Linux drivers.

Prerequisites

1. Boot Linux on the target board as described in Booting Linux. You will not need to use the serial terminal if you plan on using ssh connection.

2. Connect to the board using one of the following options:

Connect using serial console, as described in Booting Linux
Connect using ssh, as described in Connect Using SSH

3. In serial console, or ssh client console, change current folder to be /home/root/intelFPGA. This is where the application binaries are stored.

root@agilex7dksiagf014ea:~# cd /home/root/intelFPGA/
root@agilex7dksiagf014ea:~/intelFPGA#

Display Hello World Message

Run the following command to display the Hello World message on the console:

root@agilex7dksiagf014ea:~/intelFPGA# ./hello 
Hello SoC FPGA!

Exercise Soft PIO Driver for LED Control

The following LEDs are exercised:

User FPGA LED Number	Corresponding Board LED
0	D21
1	D23
2	D25

Note: User FPGA LED #3 / D27 is quickly blinking, and cannot be controlled from software.

1. In order to blink an LED in a loop, with a specific delay in ms, run the following command:

./blink <led_number> <delay_ms>

The led_number specifies the desired LED, and is a value between 0 and 3.
The delay_ms is a number that specifies the desired delay in ms between turning the LED on and off.

2. In order to turn an individual LED on or off, run the following command:

./toggle <led_number> <state>

The led_number specifies the desired LED, and is a value between 0 and 3.
The state needs to be 0 to turn the LED off, and 1 to turn the LED on.

3. In order to scroll the FPGA LEDs with a specific delay, please run the following command:

./scroll_client <delay>

The delay specifies the desired scrolling behavior:

delay > 0 - specify new scrolling delay in ms, and start scrolling
delay < 0 - stop scrolling
delay = 0 - display current scroll delay

Register Interrupts and Call Interrupt Service Routine

The following are exercised:

User FPGA DIP switches
- SW2.SW0
- SW2.SW1
- SW2.SW2
- SW2.SW3
User FPGA push buttons
- 0: S1
- 1: S2
- 2: S3
- 3: S4

In order to register an interrupt handler to a specific GPIO, you will first need to determine the GPIO number used.

1. Open the Linux Device Tree socfpga_agilex7_ghrd.dtsi file and look up the labels for the DIP switches and Push button GPIOs:

		button_pio: gpio@f9001060 {
				compatible = "altr,pio-1.0";
				reg = <0xf9001060 0x10>;
				interrupt-parent = <&intc>;	
				interrupts = <0 18 4>;
				altr,gpio-bank-width = <4>;
				altr,interrupt-type = <2>;      
				#gpio-cells = <2>;
				gpio-controller;
		};

		dipsw_pio: gpio@f9001070 {
				compatible = "altr,pio-1.0";
				reg = <0xf9001070 0x10>;
				interrupt-parent = <&intc>;	
				interrupts = <0 17 4>;
				altr,gpio-bank-width = <4>;
				altr,interrupt-type = <3>;      
				#gpio-cells = <2>;
				gpio-controller;
		};

2. Run the following to determine the GPIO numbers for the DIP switches

root@agilex7dksiagf014ea:~/intelFPGA#  grep -r "gpio@f9001070" /sys/class/gpio/gpiochip*/label 
/sys/class/gpio/gpiochip1928/label:/soc/gpio@f9001070

This means that the GPIOs 1928 .. 1931 are allocated to the DIP switches (there are 4 of them).

3. Run the followinig to determine the GPIO numbers for the pushbuttons

root@agilex7dksiagf014ea:~/intelFPGA# grep -r "gpio@f9001060" /sys/class/gpio/gpiochip*/label
/sys/class/gpio/gpiochip1960/label:/soc/gpio@f9001060

This means that the GPIOs 1960 … 1963 are allocated to the push buttons (there are 4 of them).

4. Register interrupt for one of the dipswiches, using the appropriate GPIO number, as determined in a previous step:

root@agilex7dksiagf014ea:~/intelFPGA# modprobe gpio_interrupt gpio_number=1928 intr_type=3
[  893.594901] gpio_interrupt: loading out-of-tree module taints kernel.
[  893.602212] Interrupt for GPIO:1928
[  893.602212]  registered

5. Toggle the dipswitch a few times, you will see messages from the interrupt handler

[  933.872016] Interrupt happened at gpio:1028
[  936.630233] Interrupt happened at gpio:1928
[  938.737038] Interrupt happened at gpio:1928
[  939.951513] Interrupt happened at gpio:1928

6. Remove the driver

root@agilex7dksiagf014ea:~/intelFPGA# rmmod gpio_interrupt

7. Register the pushbutton interrupt, using the appropriate GPIO number as determine on a previous step

root@agilex7dksiagf014ea:~/intelFPGA# modprobe gpio_interrupt gpio_number=1960 intr_type=2
[ 1138.025297] Interrupt for GPIO:1960
[ 1138.025297]  registered

8. Push the pusbutton a few times, you will see interrupt handler messages

[ 1141.672192] Interrupt happened at gpio:1960
[ 1142.110673] Interrupt happened at gpio:1960
[ 1142.499468] Interrupt happened at gpio:1960
[ 1142.884199] Interrupt happened at gpio:1960

9. Once done, remove the handler

root@agilex7dksiagf014ea:~/intelFPGA# rmmod gpio_interrupt

Note: If you are on the ssh console, you will need to run the program dmesg after pressing the button in order to see the messages:

root@agilex7dksiagf014ea:~/intelFPGA# dmesg

System Check Application

System check application provides a glance of system status of basic peripherals such as:

USB: USB device driver
Network IP (IPv4): Network IP address
HPS LEDs: HPS LED state
FPGA LEDs: FPGA LED state

Run the application by issuing the following command:

root@agilex7dksiagf014ea:~/intelFPGA# ./syschk

The application will look as follows, press 'q' to exit:

                                                                          ALTERA SYSTEM CHECK

lo                    : 127.0.0.1                                             usb1                  : DWC OTG Controller
eth0                  : 192.168.1.163
                                                                              serial@ffc02100       : disabled
fpga_led2             : OFF                                                   serial@ffc02000       : okay
hps_led2              : OFF
fpga_led0             : OFF
hps_led0              : OFF
fpga_led3             : OFF
fpga_led1             : OFF
hps_led1              : OFF

Connecting to Board Web Server and SSH Client

The GSRD includes a web server running on the target board that can be used to exercise some of the board features:

Turning LEDs ON and OFF
Scrolling LEDs in a sequence
Displaying the current status of the LEDs

The web page served by the web server also contains links to some relevant information on the Intel website.

Connect to Web Server

1. Boot Linux as described in Booting Linux.

2. Determine the IP address of the board using 'ifconfig' as shown above. Note there will be network interfaces of them, either can be used.

3. Open a web browser on the host PC and type http:// on the address box, then type the IP of your board and hit Enter.

4. Scroll the webpage down to the section named Interacting with Agilex SoC Development Kit.

You will be able to perform the following actions:

See which LEDs are ON and which are off in the LED Status. Note that if the LEDs are setup to be scrolling, the displayed scrolling speed will not match the actual scrolling speed on the board.
Stop LEDs from scrolling, by clicking START and STOP buttons. The delay between LEDs turning ON and OFF is set in the LED Lightshow box.
Turn individual LEDs ON and OFF with the ON and OFF buttons. Note that this action is only available when the LED scrolling/lightshow is stopped.
Blink individual LEDs by typing a delay value in ms then clicking the corresponding BLINK button. Note that this action is only available when the LED scrolling/lightshow is stopped.

Connect Using SSH

1. The lower bottom of the web page presents instructions on how to connect to the board using an SSH connection.

2. If the SSH client is not installed on your host computer, you can install it by running the following command on CentOS:

$ sudo yum install openssh-clients

or the following command on Ubuntu:

$ sudo apt-get install openssh-client

3. Connect to the board, and run some commands, such as pwd, ls and uname to see Linux in action.

Building the GSRD for the DK-SI-AGF014EA Version

Important Note: The instructions from this section build the latest version of the GSRD. Refer to Latest Source Code Release Contents - Branches and Commit IDs for component version information.

Build Flow

The following diagram illustrates the full build flow for the GSRD based on source code from GitHub.

The current build flow creates a single boot image which is able to boot in different board configurations (either using OOBE or eMMC/NAND daughter card). For more information about how this single boot image is created, please refer to the following article: https://rocketboards.org/foswiki/Documentation/SingleImageBoot

Setting up Environment

Create a top folder for this example, as the rest of the commands assume this location:

sudo rm -rf agilex_gsrd
mkdir agilex_gsrd
cd agilex_gsrd
export TOP_FOLDER=$(pwd)

Download the compiler toolchain, add it to the PATH variable, to be used by the GHRD makefile to build the HPS Debug FSBL:

cd $TOP_FOLDER
wget https://developer.arm.com/-/media/Files/downloads/gnu/11.2-2022.02/binrel/\
gcc-arm-11.2-2022.02-x86_64-aarch64-none-linux-gnu.tar.xz
tar xf gcc-arm-11.2-2022.02-x86_64-aarch64-none-linux-gnu.tar.xz
rm -f gcc-arm-11.2-2022.02-x86_64-aarch64-none-linux-gnu.tar.xz
export PATH=`pwd`/gcc-arm-11.2-2022.02-x86_64-aarch64-none-linux-gnu/bin:$PATH
export ARCH=arm64
export CROSS_COMPILE=aarch64-none-linux-gnu-

Building the Hardware Design

Use the following commands to build the hardware design:

cd $TOP_FOLDER
rm -rf ghrd-socfpga agilex_soc_devkit_ghrd
git clone -b QPDS23.4_REL_GSRD_PR https://github.com/altera-opensource/ghrd-socfpga
mv ghrd-socfpga/agilex_soc_devkit_ghrd .
rm -rf ghrd-socfpga
cd agilex_soc_devkit_ghrd
~/intelFPGA_pro/23.4/nios2eds/nios2_command_shell.sh make scrub_clean_all
~/intelFPGA_pro/23.4/nios2eds/nios2_command_shell.sh make generate_from_tcl
~/intelFPGA_pro/23.4/nios2eds/nios2_command_shell.sh make all
cd ..

The following files are created:

$TOP_FOLDER/agilex_soc_devkit_ghrd/output_files/ghrd_agfb014r24b2e2v.sof - FPGA configuration file, without HPS FSBL
$TOP_FOLDER/agilex_soc_devkit_ghrd/software/hps_debug/hps_debug.ihex - HPS Debug FSBL
$TOP_FOLDER/agilex_soc_devkit_ghrd/output_files/ghrd_agfb014r24b2e2v_hps_debug.sof - FPGA configuration file, with HPS Debug FSBL

Building Core RBF

Create the Core RBF file to be used in the rootfs created by Yocto by using the HPS Debug SOF built by the GHRD makefile:

cd $TOP_FOLDER
rm -f *jic* *rbf*
~/intelFPGA_pro/23.4/nios2eds/nios2_command_shell.sh \
  quartus_pfg -c agilex_soc_devkit_ghrd/output_files/ghrd_agfb014r24b2e2v_hps_debug.sof \
  ghrd_agfb014r24b2e2v.jic \
  -o device=MT25QU02G \
  -o flash_loader=AGFB014R24B2E2V \
  -o mode=ASX4 \
  -o hps=1
rm ghrd_agfb014r24b2e2v.hps.jic

The following files will be created:

$TOP_FOLDER/ghrd_agfb014r24b2e2v.core.rbf - HPS First configuration bitstream, phase 2: FPGA fabric

Note we are also creating an HPS JIC file, but we are discarding it, as it has the HPS Debug FSBL, while the final image needs to have the U-Boot SPL created by the Yocto recipes.

Setting Up Yocto Build System

1. First, make sure you have Yocto system requirements met: https://docs.yoctoproject.org/3.4.1/ref-manual/system-requirements.html#supported-linux-distributions.

The command to install the required packages on Ubuntu 20.04 is:

sudo apt-get update
sudo apt-get upgrade
sudo apt-get install openssh-server mc libgmp3-dev libmpc-dev gawk wget git diffstat unzip texinfo gcc \
build-essential chrpath socat cpio python3 python3-pip python3-pexpect xz-utils debianutils iputils-ping \
python3-git python3-jinja2 libegl1-mesa libsdl1.2-dev pylint3 xterm python3-subunit mesa-common-dev zstd \
liblz4-tool git fakeroot build-essential ncurses-dev xz-utils libssl-dev bc flex libelf-dev bison xinetd \
tftpd tftp nfs-kernel-server libncurses5 libc6-i386 libstdc++6:i386 libgcc++1:i386 lib32z1 \
device-tree-compiler curl mtd-utils u-boot-tools net-tools swig -y

On Ubuntu 20.04 you will also need to point the /bin/sh to /bin/bash, as the default is a link to /bin/dash:

sudo ln -sf /bin/bash /bin/sh

Note: You can also use a Docker container to build the Yocto recipes, refer to https://rocketboards.org/foswiki/Documentation/DockerYoctoBuild for details. When using a Docker container, it does not matter what Linux distribution or packages you have installed on your host, as all dependencies are provided by the Docker container.

2. Clone the Yocto script and prepare the build:

cd $TOP_FOLDER
rm -rf gsrd_socfpga
git clone -b nanbield https://github.com/altera-opensource/gsrd_socfpga
cd gsrd_socfpga
. agilex7_dk_si_agf014ea-gsrd-build.sh
build_setup

Note: Run the following commands to set up again the yocto build environments, if you closed the current window (for example when rebooting the Linux host) and want to resume the next steps:

cd $TOP_FOLDER/gsrd_socfpga
. ./poky/oe-init-build-env agilex-gsrd-rootfs/

Customize Yocto Build

1. Copy the rebuilt files to $WORKSPACE/meta-intel-fpga-refdes/recipes-bsp/ghrd/files using the following names, as expected by the yocto recipes:

agilex7_dk_si_agf014ea_gsrd_ghrd.core.rbf
agilex7_dk_si_agf014ea_nand_ghrd.core.rbf: not applicable
agilex7_dk_si_agf014ea_pr_ghrd.core.rbf: not applicable
agilex7_dk_si_agf014ea_pr_persona0.rbf: not applicable
agilex7_dk_si_agf014ea_pr_persona1.rbf: not applicable

In our case we just copy the core.ghrd file in the Yocto recipe location:

CORE_RBF=$WORKSPACE/meta-intel-fpga-refdes/recipes-bsp/ghrd/files/agilex7_dk_si_agf014ea_gsrd_ghrd.core.rbf
ln -s $TOP_FOLDER/ghrd_agfb014r24b2e2v.core.rbf $CORE_RBF

2. In the Yocto recipe $WORKSPACE/meta-intel-fpga-refdes/recipes-bsp/ghrd/hw-ref-design.bb modify the agilex_gsrd_code file location:

SRC_URI:agilex7_dk_si_agf014ea ?= "\
      ${GHRD_REPO}/agilex7_dk_si_agf014ea_gsrd_${ARM64_GHRD_CORE_RBF};name=agilex7_dk_si_agf014ea_gsrd_core \
      ${GHRD_REPO}/agilex7_dk_si_agf014ea_nand_${ARM64_GHRD_CORE_RBF};name=agilex7_dk_si_agf014ea_nand_core \
      ${GHRD_REPO}/agilex7_dk_si_agf014ea_pr_${ARM64_GHRD_CORE_RBF};name=agilex7_dk_si_agf014ea_pr_core \
      ${GHRD_REPO}/agilex7_dk_si_agf014ea_pr_persona0.rbf;name=agilex7_dk_si_agf014ea_pr_persona0 \
      ${GHRD_REPO}/agilex7_dk_si_agf014ea_pr_persona1.rbf;name=agilex7_dk_si_agf014ea_pr_persona1 \
      "

to look like this:

SRC_URI:agilex7_dk_si_agf014ea ?= "\
      file://agilex7_dk_si_agf014ea_gsrd_ghrd.core.rbf;sha256sum=xxxxxxxxx \
      ${GHRD_REPO}/agilex7_dk_si_agf014ea_nand_${ARM64_GHRD_CORE_RBF};name=agilex7_dk_si_agf014ea_nand_core \
      ${GHRD_REPO}/agilex7_dk_si_agf014ea_pr_${ARM64_GHRD_CORE_RBF};name=agilex7_dk_si_agf014ea_pr_core \
      ${GHRD_REPO}/agilex7_dk_si_agf014ea_pr_persona0.rbf;name=agilex7_dk_si_agf014ea_pr_persona0 \
      ${GHRD_REPO}/agilex7_dk_si_agf014ea_pr_persona1.rbf;name=agilex7_dk_si_agf014ea_pr_persona1 \
      "

using the following commands:

OLD_URI="\${GHRD_REPO}\/agilex7_dk_si_agf014ea_gsrd_\${ARM64_GHRD_CORE_RBF};name=agilex7_dk_si_agf014ea_gsrd_core"
CORE_SHA=$(sha256sum $CORE_RBF | cut -f1 -d" ")
NEW_URI="file:\/\/agilex7_dk_si_agf014ea_gsrd_ghrd.core.rbf;sha256sum=$CORE_SHA"
sed -i "s/$OLD_URI/$NEW_URI/g" $WORKSPACE/meta-intel-fpga-refdes/recipes-bsp/ghrd/hw-ref-design.bb

3. In the same Yocto recipe delete the old SHA256 checksum for the file:

SRC_URI[agilex7_dk_si_agf014ea_gsrd_core.sha256sum] = "5d633ee561d5cc8c22b51211a144654fdc0be47ee14b07ac134074cbff84eb8b"

by using the following commands:

sed -i "/agilex7_dk_si_agf014ea_gsrd_core\.sha256sum/d" $WORKSPACE/meta-intel-fpga-refdes/recipes-bsp/ghrd/hw-ref-design.bb

4. Optionally change the following files in $WORKSPACE/meta-intel-fpga-refdes/recipes-bsp/u-boot/files/:

uboot.txt - distroboot script
uboot_script.its - its file for creating FIT image from the above script

5. Optionally change the following file in $WORKSPACE/meta-intel-fpga-refdes/recipes-kernel/linux/linux-socfpga-lts:

fit_kernel_agilex7_dk_si_agf014ea.its - its file for creating the kernel.itb image, containing by default:
- Kernel
- Device trees for SD, NAND and PR board configurations
- Core RBF files for SD, NAND and PR board configurations
- Board configurations for SD, NAND and PR cases

Build Yocto

Build Yocto:

bitbake_image

Gather files:

package

Once the build is completed successfully, you will see the following two folders are created:

agilex7_dk_si_agf014ea-gsrd-rootfs: area used by OpenEmbedded build system for builds. Description of build directory structure - https://docs.yoctoproject.org/ref-manual/structure.html#the-build-directory-build
agilex7_dk_si_agf014ea-gsrd-images: the build script copies here relevant files built by Yocto from the agilex7_dk_si_agf014ea-gsrd-rootfs/tmp/deploy/images/agilex folder, but also other relevant files.

The two most relevant files created in the $TOP_FOLDER/gsrd_socfpga/agilex7_dk_si_agf014ea-gsrd-images folder are:

File	Description
sdimage.tar.gz	SD Card Image
u-boot-agilex-socdk-gsrd-atf/u-boot-spl-dtb.hex	U-Boot SPL Hex file

Building QSPI Flash Image

The QSPI image will contain the FPGA configuration data and the HPS FSBL and it can be built using the following command:

cd $TOP_FOLDER
rm -f *jic* *rbf*
~/intelFPGA_pro/23.4/nios2eds/nios2_command_shell.sh \
  quartus_pfg -c agilex_soc_devkit_ghrd/output_files/ghrd_agfb014r24b2e2v.sof \
  ghrd_agfb014r24b2e2v.jic \
  -o hps_path=gsrd_socfpga/agilex7_dk_si_agf014ea-gsrd-images/u-boot-agilex7-socdk-gsrd-atf/u-boot-spl-dtb.hex \
  -o device=MT25QU02G \
  -o flash_loader=AGFB014R24B2E2V \
  -o mode=ASX4 \
  -o hps=1

The following files will be created:

$TOP_FOLDER/ghrd_agfb014r24b2e2v.hps.jic - Flash image for HPS First configuration bitstream, phase 1: HPS and DDR
$TOP_FOLDER/ghrd.core.rbf - HPS First configuration bitstream, phase 2: FPGA fabric, discarded, as we already have it on the SD card

Booting from QSPI for the DK-SI-AGF014EA Version

This section presents how to boot the Agilex SoC from QSPI, with the binaries build with 23.2 release.

The instructions from this section build the latest version of the GSRD. Refer to Latest Source Code Release Contents - Branches and Commit IDs for component version information.

Much of the same binaries as when booting from SD card can be used to boot from QSPI, because:

The QSPI resides on the DevKit board, and not on the HPS daughtercard, so there are no board changes:
- The same GHRD configuration can be used
- The same U-Boot devce tree can be used
- The same Linux device tree can be used
U-Boot uses distroboot, which will try first booting from SD/MMC, then from QSPI, then from NAND, so the same U-Boot can be used.

As the QSPI has a much smaller size than the SD card (256MB vs 2GB) the rootfs is smaller, and less functionality is provided. The purpose of this section is just to show Linux booting.

Note: The HPS speed for accessing SDM QSPI is limited to ~8MB/s. It is up to you to decide whether this level of performance is sufficient for your application. If not, it is recommended you use an SD card or eMMC device to store the HPS components such as the rootfs. Note that the QSPI speed limitation does not apply when SDM accesses the QSPI, it is just for HPS accessing SDM QSPI.

QSPI Flash Layout

MTD Partition	UBI Volume	Volume Name	Type	Image/File		Size
0 (qspi_uboot)	N/A	N/A	RAW	bitstream (FPGA image, SDM firmware)		64MB
0 (qspi_uboot)	N/A	N/A	RAW	u-boot.itb		2MB
1 (qspi_root)	0	env	UBI	u-boot.env	root.ubi	256KB
	1	script	UBI	u-boot.scr		128KB
	2	kernel	UBI	kernel.itb		24MB
	3	dtb	UBI	kernel.dtb		256KB
	4	rootfs	UBIFS	rootfs.ubifs		160MB

Creating the QSPI Flash Image

1. Create a folder to contain all the qspi binaries, and create symlinks to actual location for all files:

cd $TOP_FOLDER
rm -rf qspi-boot && mkdir qspi-boot && cd qspi-boot
ln -s $TOP_FOLDER/agilex_soc_devkit_ghrd/output_files/ghrd_agfb014r24b2e2v.sof fpga.sof
ln -s $TOP_FOLDER/gsrd_socfpga/agilex7_dk_si_agf014ea-gsrd-images/u-boot-agilex7-socdk-gsrd-atf/u-boot-spl-dtb.hex spl.hex
ln -s $TOP_FOLDER/gsrd_socfpga/agilex7_dk_si_agf014ea-gsrd-images/u-boot-agilex7-socdk-gsrd-atf/boot.scr.uimg .
ln -s $TOP_FOLDER/gsrd_socfpga/agilex7_dk_si_agf014ea-gsrd-images/kernel.itb .
ln -s $TOP_FOLDER/gsrd_socfpga/agilex7_dk_si_agf014ea-gsrd-images/console-image-minimal-agilex7_nor.ubifs rootfs.ubifs

2. Create U-Boot image:

cd $TOP_FOLDER/qspi-boot
cp $TOP_FOLDER/gsrd_socfpga/agilex7_dk_si_agf014ea-gsrd-images/u-boot-agilex7-socdk-gsrd-atf/u-boot.itb .
uboot_part_size=2*1024*1024
uboot_size=`wc -c < u-boot.itb`
uboot_pad="$((uboot_part_size-uboot_size))"
truncate -s +$uboot_pad u-boot.itb
mv u-boot.itb u-boot.bin

4. Create hps.ubi file:

cd $TOP_FOLDER/qspi-boot
cat <ubinize.cfg
[env]
mode=ubi
vol_id=0
vol_name=env
vol_size=256KiB
vol_type=dynamic

[script]
mode=ubi
image=boot.scr.uimg
vol_id=1
vol_name=script
vol_size=128KiB
vol_type=dynamic

[kernel]
mode=ubi
image=kernel.itb
vol_id=2
vol_name=kernel
vol_size=24MiB
vol_type=dynamic

[dtb]
mode=ubi
vol_id=3
vol_name=dtb
vol_size=256KiB
vol_type=dynamic

[rootfs]
mode=ubi
image=rootfs.ubifs
vol_id=4
vol_name=rootfs
vol_type=dynamic
vol_size=160MiB
vol_flag=autoresize

EOT
ubinize -o root.ubi -p 65536 -m 1 -s 1 ubinize.cfg
ln -s root.ubi hps.bin

5. Create the QSPI image using the provided Quartus Programming File Generator (PFG) file:

cd $TOP_FOLDER/qspi-boot
wget https://rocketboards.org/foswiki/pub/Documentation/AgilexSoCGSRD/flash_image_qspi.pfg
~/intelFPGA_pro/23.4/nios2eds/nios2_command_shell.sh quartus_pfg -c flash_image_qspi.pfg

Creating the Programming File Generator File

This section presents how to manually re-create the PFG file provided at https://rocketboards.org/foswiki/pub/Documentation/AgilexSoCGSRD/flash_image_qspi.pfg.

1. Start Quartus Programming File Generator GUI:

cd $TOP_FOLDER/qspi-boot
~/intelFPGA_pro/23.4/nios2eds/nios2_command_shell.sh qpfgw &

2. In PFG Output Files tab:

Select Device Family as "Agillex"
Select Configuration Mode as "Active Serial x4"
Edit Name as "flash_image"
Check JTAG Indirect Configuration File (.jic)
Check Memory Map File (.map)

3. In PFG Input Files tab:

Click Add Bitstream", then browse to "fpga.sof" link, and add click *Open to add it.
Click Bitstream_1>fpga.sof then click Properties the click HPS Bootloader, browse to "spl.hex" then click Open to add it.
Note: By the time the fpga.sof file is read the following error is displayed, this was addressed by adding the spl.hex file to the Bitstream: File fpga.sof is incomplete- HPS is present but bootloader information is missing.
Click Add Raw Data then change the extension filter to .bin then browse to "u-boot.bin" and click Open to add it.
Click on the "u-boot.bin" then click "*Prpperties*" then select Bit swap option to "On"
Repeat the above 2 steps for the following files:
- hps.bin

The Input Files tab will now look something like this:

4. In the PFG Configuration Device tab:

Click Add Device, select the Micron MT25QU02G device then click Add
Click the MT25QU02G device, then click Add Partition, select the options as following then click OK:

Click the MT25QU02G device, then click Add Partition, select the options as following then click OK:

Repeat the above step for the rest of binary files, choosing the following offsets:
- hps: 0x04200000
Click Flash Loader > Select then browse to the device used on the devkit then click OK:

The Configuration Device tab will now look something like this:

3. Go to File > Save As and save the configuration file as "flash_image_qspi.pfg".

4. [Optional] Open the file "flash_image_qspi.pfg" with a text editor and change absolute paths to relative paths.

The file will look like this:

<pfg version="1">
    <settings custom_db_dir="./" mode="ASX4"/>
    <output_files>
        <output_file name="flash_image" hps="1" directory="./" type="PERIPH_JIC">
            <file_options/>
            <secondary_file type="MAP" name="flash_image_jic">
                <file_options/>
            </secondary_file>
            <flash_device_id>Flash_Device_1</flash_device_id>
        </output_file>
    </output_files>
    <bitstreams>
        <bitstream id="Bitstream_1">
            <path signing="OFF" finalize_encryption="0" hps_path="spl.hex">fpga.sof</path>
        </bitstream>
    </bitstreams>
    <raw_files>
        <raw_file bitswap="1" type="RBF" id="Raw_File_1">u-boot.bin</raw_file>
        <raw_file bitswap="1" type="RBF" id="Raw_File_2">hps.bin</raw_file>
    </raw_files>
    <flash_devices>
        <flash_device type="MT25QU02G" id="Flash_Device_1">
            <partition reserved="1" fixed_s_addr="1" s_addr="0x00000000" e_addr="0x001FFFFF" fixed_e_addr="1" id="BOOT_INFO" size="0"/>
            <partition reserved="0" fixed_s_addr="0" s_addr="auto" e_addr="auto" fixed_e_addr="0" id="P1" size="0"/>
            <partition reserved="0" fixed_s_addr="0" s_addr="0x04000000" e_addr="auto" fixed_e_addr="0" id="u-boot" size="0"/>
            <partition reserved="0" fixed_s_addr="0" s_addr="0x04200000" e_addr="auto" fixed_e_addr="0" id="hps" size="0"/>
        </flash_device>
        <flash_loader>AGFB014R24B</flash_loader>
    </flash_devices>
    <assignments>
        <assignment page="0" partition_id="P1">
            <bitstream_id>Bitstream_1</bitstream_id>
        </assignment>
        <assignment partition_id="u-boot">
            <raw_file_id>Raw_File_1</raw_file_id>
        </assignment>
        <assignment page="0" partition_id="hps">
            <raw_file_id>Raw_File_2</raw_file_id>
        </assignment>
    </assignments>
</pfg>

Writing the QSPI Flash Image

1. Configure MSEL to JTAG:

2. Power cycle the board

3. Write the image using the following commands:

~/intelFPGA_pro/23.4/nios2eds/nios2_command_shell.sh \
quartus_pgm -c 1 -m jtag -o "pvi;flash_image.hps.jic"

Booting Linux

1. Configure MSEL back to QSPI

2. Important: Remove SD card (or write zero to first few MBs) to confirm Linux is booting without it.

3. Power cycle. Board will boot up to Linux prompt, where you can login as 'root' without a password:

U-Boot SPL 2023.07-rc6 (Nov 20 2023 - 08:40:20 +0000)
Reset state: Cold
MPU          1200000 kHz
L4 Main        400000 kHz
L4 sys free   100000 kHz
L4 MP         200000 kHz
L4 SP         100000 kHz
SDMMC          50000 kHz
DDR: 8192 MiB
SDRAM-ECC: Initialized success with 1722 ms
QSPI: Reference clock at 400000 kHz
WDT:   Started watchdog@ffd00200 with servicing every 1000ms (10s timeout)
denali-nand-dt nand@ffb90000: timeout while waiting for irq 0x2000
denali-nand-dt nand@ffb90000: reset not completed.
Trying to boot from MMC1
** Partition 1 not valid on device 0 **
spl_register_fat_device: fat register err - -1
spl_load_image_fat: error reading image u-boot.itb, err - -1
Trying to boot from SPI
## Checking hash(es) for config board-4 … OK
## Checking hash(es) for Image atf … crc32+ OK
## Checking hash(es) for Image uboot … crc32+ OK
## Checking hash(es) for Image fdt-0 … crc32+ OK
NOTICE:  BL31: v2.9.1(release):QPDS23.4_REL_GSRD_PR
NOTICE:  BL31: Built : 07:49:14, Dec  4 2023

U-Boot 2023.07-rc6 (Nov 20 2023 - 08:40:20 +0000)socfpga_agilex

CPU:   Intel FPGA SoCFPGA Platform (ARMv8 64bit Cortex-A53)
Model: SoCFPGA Agilex SoCDK
DRAM:  2 GiB (effective 8 GiB)
Core:  29 devices, 24 uclasses, devicetree: separate
Warning: Device tree includes old 'u-boot,dm-' tags: please fix by 2023.07!
WDT:   Started watchdog@ffd00200 with servicing every 1000ms (10s timeout)
NAND:  denali-nand-dt nand@ffb90000: timeout while waiting for irq 0x2000
denali-nand-dt nand@ffb90000: reset not completed.
Failed to initialize Denali NAND controller. (error -5)
0 MiB
MMC:   dwmmc0@ff808000: 0
Loading Environment from FAT... ** No partition table - mmc 0 **
Loading Environment from UBI... denali-nand-dt nand@ffb90000: timeout while waiting for irq 0x2000
denali-nand-dt nand@ffb90000: reset not completed.
SF: Detected mt25qu02g with page size 256 Bytes, erase size 64 KiB, total 256 MiB
Could not find a valid device for ffb90000.nand.0
Read 8192 bytes from volume env to 000000007fadd740
*** Warning - bad CRC, using default environment

In:    serial0@ffc02000
Out:   serial0@ffc02000
Err:   serial0@ffc02000
Net:   
Warning: ethernet@ff800000 (eth0) using random MAC address - da:5c:96:a5:99:4a
eth0: ethernet@ff800000
Hit any key to stop autoboot:  0 
switch to partitions #0, OK
mmc0 is current device
** No partition table - mmc 0 **
Couldn't find partition mmc 0:1
SF: Detected mt25qu02g with page size 256 Bytes, erase size 64 KiB, total 256 MiB
Select Environment on UBI: OK
Saving Environment to UBI... denali-nand-dt nand@ffb90000: timeout while waiting for irq 0x2000
denali-nand-dt nand@ffb90000: reset not completed.
Could not find a valid device for nand.0
done
OK
UBI partition 'root' already selected
UBI partition 'root' already selected
No size specified → Using max size (196224)
Read 196224 bytes from volume script to 0000000005ff0000
QSPI: Running script from UBIFS
QSPI: Trying to boot script at 0x05FF0000
## Executing script at 05ff0000
crc32+ Trying to boot Linux from device qspi
Device nand0 not found!
UBI partition 'root' already selected
No size specified → Using max size (25182080)
Read 25182080 bytes from volume kernel to 0000000002000000
## Loading kernel from FIT Image at 02000000 …
   Using 'board-4' configuration
   Verifying Hash Integrity … OK
   Trying 'kernel' kernel subimage
     Description:  Linux Kernel
     Type:         Kernel Image
     Compression:  lzma compressed
     Data Start:   0x020000dc
     Data Size:    9458279 Bytes = 9 MiB
     Architecture: AArch64
     OS:           Linux
     Load Address: 0x06000000
     Entry Point:  0x06000000
     Hash algo:    crc32
     Hash value:   1f7eb084
   Verifying Hash Integrity … crc32+ OK
## Loading fdt from FIT Image at 02000000 …
   Using 'board-4' configuration
   Verifying Hash Integrity … OK
   Trying 'fdt-4' fdt subimage
     Description:  socfpga_socdk_combined
     Type:         Flat Device Tree
     Compression:  uncompressed
     Data Start:   0x0291cc58
     Data Size:    33653 Bytes = 32.9 KiB
     Architecture: AArch64
     Hash algo:    crc32
     Hash value:   6fa0865c
   Verifying Hash Integrity … crc32+ OK
   Booting using the fdt blob at 0x291cc58
Working FDT set to 291cc58
## Loading fpga from FIT Image at 02000000 …
   Trying 'fpga-4' fpga subimage
     Description:  FPGA bitstream for GHRD
     Type:         FPGA Image
     Compression:  uncompressed
     Data Start:   0x02d3d200
     Data Size:    2260992 Bytes = 2.2 MiB
     Load Address: 0x0a000000
     Hash algo:    crc32
     Hash value:   edb1ced6
   Verifying Hash Integrity … crc32+ OK
   Loading fpga from 0x02d3d200 to 0x0a000000
…FPGA reconfiguration OK!
Enable FPGA bridges
   Programming full bitstream... OK
   Uncompressing Kernel Image
   Loading Device Tree to 000000007eacd000, end 000000007ead8374 … OK
Working FDT set to 7eacd000
SF: Detected mt25qu02g with page size 256 Bytes, erase size 64 KiB, total 256 MiB
Enabling QSPI at Linux DTB...
Working FDT set to 7eacd000
libfdt fdt_path_offset() returned FDT_ERR_NOTFOUND
libfdt fdt_path_offset() returned FDT_ERR_NOTFOUND
QSPI clock frequency updated
RSU: Firmware or flash content not supporting RSU
RSU: Firmware or flash content not supporting RSU
RSU: Firmware or flash content not supporting RSU
RSU: Firmware or flash content not supporting RSU

Starting kernel …

Deasserting all peripheral resets
[    0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034]
[    0.000000] Linux version 6.1.55-altera (oe-user@oe-host) (aarch64-poky-linux-gcc (GCC) 13.2.0, GNU ld (GNU Binutils) 2.41.0.20230926) #1 SMP PREEMPT Thu Nov 16 08:12:10 UTC 2023
[    0.000000] Machine model: SoCFPGA Agilex SoCDK

…

[  262.075940] socfpga-dwmac ff802000.ethernet eth1: PHY [stmmac-1:00] driver [Marvell 88E1111] (irq=POLL)
[  262.085441] socfpga-dwmac ff802000.ethernet eth1: No Safety Features support found
[  262.095614] socfpga-dwmac ff802000.ethernet eth1: IEEE 1588-2008 Advanced Timestamp supported
[  262.107375] socfpga-dwmac ff802000.ethernet eth1: registered PTP clock
[  262.115467] socfpga-dwmac ff802000.ethernet eth1: configuring for phy/sgmii link mode
[  OK  ] Finished OpenSSH Key Generation.

Poky (Yocto Project Reference Distro) 4.3.1 agilex7dksiagf014ea ttyS0

agilex7dksiagf014ea login: root
root@agilex7dksiagf014ea:~#

Note: First time Linux is booted, the UBIFS rootfs will be initialized, the step taking approximately 3 minutes, as shown in the log below:

[    2.104767] UBIFS (ubi0:4): background thread "ubifs_bgt0_4" started, PID 120
[    2.129196] UBIFS (ubi0:4): start fixing up free space
[    5.218912] random: crng init done
[   12.262444] platform soc:leds: deferred probe pending
 … 3 minute 'gap' here ...
[  197.179502] UBIFS (ubi0:4): free space fixup complete
[  197.308165] UBIFS (ubi0:4): UBIFS: mounted UBI device 0, volume 4, name "rootfs"

On the first boot empty pages are identifies and erased, to ensure all pages are 0xFF and avoid problematic non-0xFF empty page. This is controlled by the "-F" parameter passed when creating the rootfs.ubifs image. The next boots will not have this this step. Refer to http://www.linux-mtd.infradead.org/faq/ubifs.html for more details.

Booting From NAND for the DK-SI-AGF014EA Version

This section presents how to boot the Agilex 10 SoC from NAND, including how to build all binaries.

Build instructions are the same as for standard SD or QSPI boot. The U-Boot, ATF and Linux binaries are all the same. The only difference is that the GHRD is configured for the NAND HPS Daughtercard, then recompiled.

The instructions from this section build the latest version of the GSRD. Refer to Latest Source Code Release Contents - Branches and Commit IDs for component version information.

Note: As the NAND used on the devkit has a smaller size than the SD card (1GB vs 2GB) the rootfs is smaller, and less functionality is provided. The purpose of this section is just to show Linux booting.

NAND Flash Layout

MTD Partition	UBI Volume	Volume Name	Type	Image/File		Flash Offset	Size	Size in Hex
0 (u-boot)	N/A	N/A	RAW	u-boot.itb		0x00000000	2MB	0x00200000
1 (root)	0	env	UBI	u-boot.env	root.ubi	0x00200000 onwards	256KB	0x40000
	1	script	UBI	u-boot.scr			128KB	0x00020000
	2	kernel	UBI	kernel.itb			64MB	0x04000000
	3	dtb	UBI	kernel.dtb			256KB	0x00040000
	4	rootfs	UBIFS	rootfs.ubifs			<957MB	<0x3BD70000

Setting up Environment

Create a top folder for this example, as the rest of the commands assume this location:

sudo rm -rf agilex_gsrd.nand
mkdir agilex_gsrd.nand
cd agilex_gsrd.nand
export TOP_FOLDER=$(pwd)

Download the compiler toolchain, add it to the PATH variable, to be used by the GHRD makefile to build the HPS Debug FSBL:

cd $TOP_FOLDER
wget https://developer.arm.com/-/media/Files/downloads/gnu/11.2-2022.02/binrel/\
gcc-arm-11.2-2022.02-x86_64-aarch64-none-linux-gnu.tar.xz
tar xf gcc-arm-11.2-2022.02-x86_64-aarch64-none-linux-gnu.tar.xz
rm -f gcc-arm-11.2-2022.02-x86_64-aarch64-none-linux-gnu.tar.xz
export PATH=`pwd`/gcc-arm-11.2-2022.02-x86_64-aarch64-none-linux-gnu/bin:$PATH
export ARCH=arm64
export CROSS_COMPILE=aarch64-none-linux-gnu-

Building the Hardware Design

Use the following commands to build the hardware design:

cd $TOP_FOLDER
rm -rf ghrd-socfpga agilex_soc_devkit_ghrd
git clone -b QPDS23.4_REL_GSRD_PR https://github.com/altera-opensource/ghrd-socfpga
mv ghrd-socfpga/agilex_soc_devkit_ghrd .
rm -rf ghrd-socfpga
cd agilex_soc_devkit_ghrd
export DAUGHTER_CARD=devkit_dc_nand
~/intelFPGA_pro/23.4/nios2eds/nios2_command_shell.sh make scrub_clean_all
~/intelFPGA_pro/23.4/nios2eds/nios2_command_shell.sh make generate_from_tcl
# fix issues in top level verilog file, if not already fixed
sed -i 's/fpga_reset_n,/fpga_reset_n/g' ghrd_agilex_top.v
~/intelFPGA_pro/23.4/nios2eds/nios2_command_shell.sh make all
unset DAUGHTER_CARD
unset QUARTUS_DEVICE
cd ..

The following files are created:

$TOP_FOLDER/agilex_soc_devkit_ghrd/output_files/ghrd_agfb014r24b2e2v.sof - FPGA configuration file, without HPS FSBL
$TOP_FOLDER/agilex_soc_devkit_ghrd/software/hps_debug/hps_debug.ihex - HPS Debug FSBL
$TOP_FOLDER/agilex_soc_devkit_ghrd/output_files/ghrd_agfb014r24b2e2v_hps_debug.sof - FPGA configuration file, with HPS Debug FSBL

Building Core RBF

Create the Core RBF file to be used in the rootfs created by Yocto by using the HPS Debug SOF built by the GHRD makefile:

cd $TOP_FOLDER
rm -f *jic* *rbf*
~/intelFPGA_pro/23.4/nios2eds/nios2_command_shell.sh \
  quartus_pfg -c agilex_soc_devkit_ghrd/output_files/ghrd_agfb014r24b2e2v_hps_debug.sof \
  ghrd_agfb014r24b2e2v.jic \
  -o device=MT25QU02G \
  -o flash_loader=AGFB014R24B2E2V \
  -o mode=ASX4 \
  -o hps=1
rm ghrd_agfb014r24b2e2v.hps.jic

The following files will be created:

$TOP_FOLDER/ghrd_agfb014r24b2e2v.core.rbf - HPS First configuration bitstream, phase 2: FPGA fabric

Note we are also creating an HPS JIC file, but we are discarding it, as it has the HPS Debug FSBL, while the final image needs to have the U-Boot SPL created by the Yocto recipes.

Setting Up Yocto Build System

1. First, make sure you have Yocto system requirements met: https://docs.yoctoproject.org/3.4.1/ref-manual/system-requirements.html#supported-linux-distributions.

The command to install the required packages on Ubuntu is:

sudo apt install gawk wget git diffstat unzip texinfo gcc build-essential chrpath \
socat cpio python3 python3-pip python3-pexpect xz-utils debianutils iputils-ping \
python3-git python3-jinja2 libegl1-mesa libsdl1.2-dev pylint3 xterm python3-subunit \
mesa-common-dev zstd liblz4-tool

2. Clone the Yocto script and prepare the build:

cd $TOP_FOLDER
rm -rf gsrd_socfpga
git clone -b nanbield https://github.com/altera-opensource/gsrd_socfpga
cd gsrd_socfpga
. agilex7_dk_si_agf014ea-gsrd-build.sh
build_setup

Note: Run the following commands to set up again the yocto build environments, if you closed the current window (for example when rebooting the Linux host) and want to resume the next steps:

cd $TOP_FOLDER/gsrd_socfpga
. ./poky/oe-init-build-env agilex-gsrd-rootfs/

Customize Yocto Build

1. Copy the rebuilt files to $WORKSPACE/meta-intel-fpga-refdes/recipes-bsp/ghrd/files using the following names, as expected by the yocto recipes:

agilex7_dk_si_agf014ea_gsrd_ghrd.core.rbf: not applicable
agilex7_dk_si_agf014ea_nand_ghrd.core.rbf
agilex7_dk_si_agf014ea_pr_ghrd.core.rbf: not applicable
agilex7_dk_si_agf014ea_pr_persona0.rbf: not applicable
agilex7_dk_si_agf014ea_pr_persona1.rbf: not applicable

In our case we just copy the core.ghrd file in the Yocto recipe location:

CORE_RBF=$WORKSPACE/meta-intel-fpga-refdes/recipes-bsp/ghrd/files/agilex7_dk_si_agf014ea_nand_ghrd.core.rbf
ln -s $TOP_FOLDER/ghrd_agfb014r24b2e2v.core.rbf $CORE_RBF

2. In the Yocto recipe $WORKSPACE/meta-intel-fpga-refdes/recipes-bsp/ghrd/hw-ref-design.bb modify the agilex_gsrd_code file location:

SRC_URI:agilex7_dk_si_agf014ea ?= "\
      ${GHRD_REPO}/agilex7_dk_si_agf014ea_gsrd_${ARM64_GHRD_CORE_RBF};name=agilex7_dk_si_agf014ea_gsrd_core \
      ${GHRD_REPO}/agilex7_dk_si_agf014ea_nand_${ARM64_GHRD_CORE_RBF};name=agilex7_dk_si_agf014ea_nand_core \
      ${GHRD_REPO}/agilex7_dk_si_agf014ea_pr_${ARM64_GHRD_CORE_RBF};name=agilex7_dk_si_agf014ea_pr_core \
      ${GHRD_REPO}/agilex7_dk_si_agf014ea_pr_persona0.rbf;name=agilex7_dk_si_agf014ea_pr_persona0 \
      ${GHRD_REPO}/agilex7_dk_si_agf014ea_pr_persona1.rbf;name=agilex7_dk_si_agf014ea_pr_persona1 \
      "

to look like this:

SRC_URI:agilex7_dk_si_agf014ea ?= "\
      ${GHRD_REPO}/agilex7_dk_si_agf014ea_gsrd_${ARM64_GHRD_CORE_RBF};name=agilex7_dk_si_agf014ea_gsrd_core \
      file://agilex7_dk_si_agf014ea_nand_ghrd.core.rbf;sha256sum=xxxxxxxxxxxxx \
      ${GHRD_REPO}/agilex7_dk_si_agf014ea_pr_${ARM64_GHRD_CORE_RBF};name=agilex7_dk_si_agf014ea_pr_core \
      ${GHRD_REPO}/agilex7_dk_si_agf014ea_pr_persona0.rbf;name=agilex7_dk_si_agf014ea_pr_persona0 \
      ${GHRD_REPO}/agilex7_dk_si_agf014ea_pr_persona1.rbf;name=agilex7_dk_si_agf014ea_pr_persona1 \
      "

using the following commands:

OLD_URI="\${GHRD_REPO}\/agilex7_dk_si_agf014ea_nand_\${ARM64_GHRD_CORE_RBF};name=agilex7_dk_si_agf014ea_nand_core"
CORE_SHA=$(sha256sum $CORE_RBF | cut -f1 -d" ")
NEW_URI="file:\/\/agilex7_dk_si_agf014ea_nand_ghrd.core.rbf;sha256sum=$CORE_SHA"
sed -i "s/$OLD_URI/$NEW_URI/g" $WORKSPACE/meta-intel-fpga-refdes/recipes-bsp/ghrd/hw-ref-design.bb

3. In the same Yocto recipe delete the old SHA256 checksum for the file:

SRC_URI[agilex7_dk_si_agf014ea_nand_core.sha256sum] = "f7a9a7f60f6c1c1c0197292573c844be625d9cd3e96c1c1105e1a6057aad699c"

by using the following command:

sed -i "/agilex7_dk_si_agf014ea_nand_core\.sha256sum/d" $WORKSPACE/meta-intel-fpga-refdes/recipes-bsp/ghrd/hw-ref-design.bb

4. Optionally change the following files in $WORKSPACE/meta-intel-fpga-refdes/recipes-bsp/u-boot/files/:

uboot.txt - distroboot script
uboot_script.its - its file for creating FIT image from the above script

5. Optionally change the following file in $WORKSPACE/meta-intel-fpga-refdes/recipes-kernel/linux/linux-socfpga-lts:

fit_kernel_agilex7_dk_si_agf014ea.its - its file for creating the kernel.itb image, containing by default:
- Kernel
- Device trees for SD, NAND and PR board configurations
- Core RBF files for SD, NAND and PR board configurations
- Board configurations for SD, NAND and PR cases

Build Yocto

Build Yocto:

bitbake_image

Gather files:

package

Once the build is completed successfully, you will see the following two folders are created:

agilex7_dk_si_agf014ea-gsrd-rootfs: area used by OpenEmbedded build system for builds. Description of build directory structure - https://docs.yoctoproject.org/ref-manual/structure.html#the-build-directory-build
agilex7_dk_si_agf014ea-gsrd-images: the build script copies here relevant files built by Yocto from the agilex7_dk_si_agf014ea-gsrd-rootfs/tmp/deploy/images/agilex folder, but also other relevant files.

The two most relevant files created in the $TOP_FOLDER/gsrd_socfpga/agilex7_dk_si_agf014ea-gsrd-images folder are:

File	Description
gsrd-console-image-agilex7_nand.ubifs	UBI root partition image
u-boot-agilex-socdk-gsrd-atf/u-boot.itb	U-Boot FIT image
u-boot-agilex-socdk-gsrd-atf/u-boot-spl-dtb.hex	U-Boot SPL Hex file

Building QSPI Flash Image

The QSPI image will contain the FPGA configuration data and the HPS FSBL and it can be built using the following command:

cd $TOP_FOLDER
rm -f *jic* *rbf*
~/intelFPGA_pro/23.4/nios2eds/nios2_command_shell.sh \
  quartus_pfg -c agilex_soc_devkit_ghrd/output_files/ghrd_agfb014r24b2e2v.sof \
  ghrd_agfb014r24b2e2v.jic \
  -o hps_path=gsrd_socfpga/agilex7_dk_si_agf014ea-gsrd-images/u-boot-agilex7-socdk-gsrd-atf/u-boot-spl-dtb.hex \
  -o device=MT25QU02G \
  -o flash_loader=AGFB014R24B2E2V \
  -o mode=ASX4 \
  -o hps=1

The following files will be created:

$TOP_FOLDER/ghrd_agfb014r24b2e2v.hps.jic - Flash image for HPS First configuration bitstream, phase 1: HPS and DDR
$TOP_FOLDER/ghrd_agfb014r24b2e2v.core.rbf - HPS First configuration bitstream, phase 2: FPGA fabric, discarded, as we already have it on the SD card

Building NAND Binaries

1. Gather the files into a single folder, using symlinks:

cd $TOP_FOLDER
rm -rf nand-bin && mkdir nand-bin && cd nand-bin
ln -s $TOP_FOLDER/gsrd_socfpga/agilex7_dk_si_agf014ea-gsrd-images/u-boot-agilex7-socdk-gsrd-atf/boot.scr.uimg u-boot.scr
ln -s $TOP_FOLDER/gsrd_socfpga/agilex7_dk_si_agf014ea-gsrd-images/kernel.itb .
ln -s $TOP_FOLDER/gsrd_socfpga/agilex7_dk_si_agf014ea-gsrd-images/gsrd-console-image-agilex7_nand.ubifs rootfs.ubifs

2. Install mtd-tools if not already installed. On Ubuntu the command is:

sudo apt-get install mtd-tools

3. Create UBI configuration file for the root partition:

cat <<EOT >ubinize.cfg 
[env]
mode=ubi
vol_id=0
vol_name=env
vol_size=256KiB
vol_type=dynamic

[script]
mode=ubi
image=u-boot.scr
vol_id=1
vol_name=script
vol_size=128KiB 
vol_type=dynamic

[kernel]
mode=ubi
image=kernel.itb
vol_id=2
vol_name=kernel
vol_size=64MiB 
vol_type=dynamic

[dtb]
mode=ubi
vol_id=3    
vol_name=dtb   
vol_size=256KiB 
vol_type=dynamic

[rootfs]
mode=ubi
image=rootfs.ubifs
vol_id=4
vol_name=rootfs
vol_type=dynamic
vol_size=400MiB
vol_flag=autoresize
EOT

4. Create the root.ubi file:

ubinize -o root.ubi -p 128KiB -m 2048 -s 2048 ubinize.cfg

This is what the above parameters mean:

-p: physical eraseblock size of the flash
-m: minimum input/output unit size of the flash
-s: sub-pages and sub-page size, ubinize will take into account and put the VID header to same NAND page as the EC header

The following file is created:

$TOP_FOLDER/nand-bin/root.ubi

Write NAND Binaries

Write Binaries to NAND

1. Copy files to your TFTP server folder:

cp -f $TOP_FOLDER/gsrd_socfpga/agilex7_dk_si_agf014ea-gsrd-images/u-boot-agilex7-socdk-gsrd-atf/u-boot.itb<your-tftp-server-folder>
cp -f $TOP_FOLDER/nand-bin/root.ubi <your-tftp-server-folder>

2. Run U-Boot with the debugger, similar to how it is described at https://rocketboards.org/foswiki/Documentation/BuildingBootloader#Agilex_45_Run_U_45Boot_from_Debugger just change the script to use the binaries directly from $TOP_FOLDER/gsrd_socfpga/agilex7_dk_si_agf014ea-gsrd-images/u-boot-agilex7-socdk-gsrd-atf/ and use the new name for the sof: agilex_soc_devkit_ghrd/output_files/ghrd_agfb014r24b2e2v_hps_debug.sof.

3. Stop at U-Boot prompt, and run the following instructions to download and write NAND binaries to flash:

setenv autoload no
dhcp
setenv serverip <your-tftp-server-ip>

tftp $loadaddr u-boot.itb
nand erase.part u-boot
nand write $loadaddr u-boot $filesize

tftp $loadaddr root.ubi
nand erase.part clean root
nand write.trimffs $loadaddr root $filesize

Write QSPI Image

1. Power off board

2. Set MSEL to JTAG

3. Power on board

4. Write jic image to QSPI:

cd $TOP_FOLDER
~/intelFPGA_pro/23.4/nios2eds/nios2_command_shell.sh \
quartus_pgm -c 1 -m jtag -o "pvi;ghrd_agfb014r24b2e2v.hps.jic"

Boot Linux

1. Make sure board is powered off.

2. Set MSEL to QSPI

3. Power up the board.

4. Linux will boot, enter 'root' as user name to log in:

U-Boot SPL 2023.07-rc6 (Nov 20 2023 - 08:40:20 +0000)
Reset state: Cold
MPU          1200000 kHz
L4 Main        400000 kHz
L4 sys free   100000 kHz
L4 MP         200000 kHz
L4 SP         100000 kHz
SDMMC          50000 kHz
DDR: 8192 MiB
SDRAM-ECC: Initialized success with 1720 ms
QSPI: Reference clock at 400000 kHz
WDT:   Started watchdog@ffd00200 with servicing every 1000ms (10s timeout)
Trying to boot from MMC1
spl: mmc init failed with error: -5
Trying to boot from SPI
Trying to boot from NAND
## Checking hash(es) for config board-1 … OK
## Checking hash(es) for Image atf … crc32+ OK
## Checking hash(es) for Image uboot … crc32+ OK
## Checking hash(es) for Image fdt-1 … crc32+ OK
NOTICE:  BL31: v2.9.1(release):QPDS23.4_REL_GSRD_PR
NOTICE:  BL31: Built : 07:49:14, Dec  4 2023

U-Boot 2023.07-rc6 (Nov 20 2023 - 08:40:20 +0000)socfpga_agilex

CPU:   Intel FPGA SoCFPGA Platform (ARMv8 64bit Cortex-A53)
Model: SoCFPGA Agilex SoCDK
DRAM:  2 GiB (effective 8 GiB)
Core:  26 devices, 22 uclasses, devicetree: separate
Warning: Device tree includes old 'u-boot,dm-' tags: please fix by 2023.07!
WDT:   Started watchdog@ffd00200 with servicing every 1000ms (10s timeout)
NAND:  1024 MiB
MMC:   
Loading Environment from FAT... ** Bad device specification mmc 0 **
Loading Environment from UBI... SF: Detected mt25qu02g with page size 256 Bytes, erase size 64 KiB, total 256 MiB

Warning: MTD name "root" is not unique!

Warning: MTD name "root" is not unique!

Volume env not found!

** Unable to read env from root:env **
In:    serial0@ffc02000
Out:   serial0@ffc02000
Err:   serial0@ffc02000
Net:   
Warning: ethernet@ff804000 (eth2) using random MAC address - 96:b0:27:59:b9:de
eth2: ethernet@ff804000
Hit any key to stop autoboot:  0 
No MMC device available
SF: Detected mt25qu02g with page size 256 Bytes, erase size 64 KiB, total 256 MiB
Select Environment on UBI: OK
Saving Environment to UBI... Volume env not found!

** Unable to write env to root:env **
Failed (1)
QSPI: Trying to boot script at 0x05FF0000
## Executing script at 05ff0000
Wrong image format for "source" command
QSPI: SCRIPT FAILED: continuing...
Select Environment on UBI: OK
Saving Environment to UBI... done
OK
UBI partition 'root' already selected
No size specified → Using max size (253952)
Read 253952 bytes from volume script to 0000000005ff0000
NAND: Trying to boot script at 0x05FF0000
## Executing script at 05ff0000
crc32+ Trying to boot Linux from device nand
Select Environment on UBI: OK
Saving Environment to UBI... UBI partition 'root' already selected
done
OK

device nor0 , # parts = 2
 #: name    size     offset      mask_flags
 0: u-boot              0x04200000  0x00000000  0
 1: qspi_root           0x0be00000  0x04200000  0

device nand0 , # parts = 2
 #: name    size     offset      mask_flags
 0: u-boot              0x00200000  0x00000000  0
 1: root                0x3fe00000  0x00200000  0

active partition: nor0,0 - (u-boot) 0x04200000 @ 0x00000000

defaults:
mtdids  : nand0=ffb90000.nand.0
mtdparts: mtdparts=ffb90000.nand.0:2m(u-boot),-(root)
UBI partition 'root' already selected
No size specified → Using max size (67170304)
Read 67170304 bytes from volume kernel to 0000000002000000
## Loading kernel from FIT Image at 02000000 …
   Using 'board-1' configuration
   Verifying Hash Integrity … OK
   Trying 'kernel' kernel subimage
     Description:  Linux Kernel
     Type:         Kernel Image
     Compression:  lzma compressed
     Data Start:   0x020000dc
     Data Size:    9458279 Bytes = 9 MiB
     Architecture: AArch64
     OS:           Linux
     Load Address: 0x06000000
     Entry Point:  0x06000000
     Hash algo:    crc32
     Hash value:   1f7eb084
   Verifying Hash Integrity … crc32+ OK
## Loading fdt from FIT Image at 02000000 …
   Using 'board-1' configuration
   Verifying Hash Integrity … OK
   Trying 'fdt-1' fdt subimage
     Description:  socfpga_socdk_nand
     Type:         Flat Device Tree
     Compression:  uncompressed
     Data Start:   0x0290cc24
     Data Size:    33001 Bytes = 32.2 KiB
     Architecture: AArch64
     Hash algo:    crc32
     Hash value:   a173d76a
   Verifying Hash Integrity … crc32+ OK
   Booting using the fdt blob at 0x290cc24
Working FDT set to 290cc24
## Loading fpga from FIT Image at 02000000 …
   Trying 'fpga-1' fpga subimage
     Description:  FPGA bitstream for NAND
     Type:         FPGA Image
     Compression:  uncompressed
     Data Start:   0x02925080
     Data Size:    2277376 Bytes = 2.2 MiB
     Load Address: 0x0a000000
     Hash algo:    crc32
     Hash value:   eeed3f19
   Verifying Hash Integrity … crc32+ OK
   Loading fpga from 0x02925080 to 0x0a000000
…FPGA reconfiguration OK!
Enable FPGA bridges
   Programming full bitstream... OK
   Uncompressing Kernel Image
   Loading Device Tree to 000000007eacf000, end 000000007eada0e8 … OK
Working FDT set to 7eacf000
SF: Detected mt25qu02g with page size 256 Bytes, erase size 64 KiB, total 256 MiB
Enabling QSPI at Linux DTB...
Working FDT set to 7eacf000
libfdt fdt_path_offset() returned FDT_ERR_NOTFOUND
libfdt fdt_path_offset() returned FDT_ERR_NOTFOUND
QSPI clock frequency updated
RSU: Firmware or flash content not supporting RSU
RSU: Firmware or flash content not supporting RSU
RSU: Firmware or flash content not supporting RSU
RSU: Firmware or flash content not supporting RSU

Starting kernel …

Deasserting all peripheral resets
[    0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034]
[    0.000000] Linux version 6.1.55-altera (oe-user@oe-host) (aarch64-poky-linux-gcc (GCC) 13.2.0, GNU ld (GNU Binutils) 2.41.0.20230926) #1 SMP PREEMPT Thu Nov 16 08:12:10 UTC 2023
[    0.000000] Machine model: SoCFPGA Agilex SoCDK

…

[   10.139803] socfpga-dwmac ff804000.ethernet eth1: No Safety Features support found
[   10.147438] socfpga-dwmac ff804000.ethernet eth1: IEEE 1588-2008 Advanced Timestamp supported
[   10.156485] socfpga-dwmac ff804000.ethernet eth1: registered PTP clock
[   10.163674] socfpga-dwmac ff804000.ethernet eth1: configuring for phy/rgmii link mode
[  OK  ] Started Network Configuration.
[  OK  ] Reached target Network.
[  OK  ] Started Hostname Service.
[  OK  ] Finished OpenSSH Key Generation.
[   14.276900] socfpga-dwmac ff804000.ethernet eth1: Link is Up - 1Gbps/Full - flow control rx/tx
[   14.285598] IPv6: ADDRCONF(NETDEV_CHANGE): eth1: link becomes ready
[   14.309363] 8021q: 802.1Q VLAN Support v1.8

Poky (Yocto Project Reference Distro) 4.3.1 agilex7dksiagf014ea ttyS0

agilex7dksiagf014ea login: root
root@agilex7dksiagf014ea:~#

Partial Reconfiguration for the DK-SI-AGF014EA Version

Partial reconfiguration (PR) allows you to reconfigure a portion of the FPGA dynamically, while the rest of the FPGA design continues to function.

The current version of the GHRD does not allow enabling both SGMII and PR (Partial Reconfiguration) at the same time. Because of this, the GHRD needs to be recompiled with SGMII disabled and PR enabled to allow PR to be used.

This section shows how to build everything needed to demonstrate the PR scenarios. Note that most of the binaries are the same as for the other boot scenarios (SD card, QSPI, NAND) just the following files are changed:

New GHRD variant, creating different configuration bitstreams
Updated core.rbf, persona0.rbf, persona1.rbf compared to prebuilt default files used by the Yocto recipes

Reference Information

Refer to the following fore more details about Partial Reconfiguration

User Guide
- Intel Quartus Prime Pro Edition User Guide: Partial Reconfiguration
Partial Reconfiguration for Intel FPGA Devices YouTube videos:

Hardware Design

The updated GHRD contains the following components which enable PR:

A PR region was created in the FPGA fabric, with the following associated IP
- PR Freeze Controller - to help control the PR
- Avalon-MM PR Freeze Bridge - to help isolate the IP in the PR region during the PR process
The base revision of the project has the following in the PR region:
- SysID located at 0xF900_0800: with id=0xfacecafe
- OCRAM located at 0xF900_0900
An alternate revision of the project contains the following in the PR region:
- SysID located at 0xF900_0900: with id=0xcafeface
- OCRAM located at 0xF900_0800

The following diagram presents an overview of the PR region and associated IP and how it is connected to HPS:

Throughout this page, the content of the PR region for the base revision is called "persona0" while the content of the PR region for the other revision is called "persona1". The diagram below illustrates the differences between the two personas:

Setting up Environment

Create a top folder for this example, as the rest of the commands assume this location:

sudo rm -rf agilex_gsrd.pr
mkdir agilex_gsrd.pr
cd agilex_gsrd.pr
export TOP_FOLDER=$(pwd)

Download the compiler toolchain, add it to the PATH variable, to be used by the GHRD makefile to build the HPS Debug FSBL:

cd $TOP_FOLDER
wget https://developer.arm.com/-/media/Files/downloads/gnu/11.2-2022.02/binrel/\
gcc-arm-11.2-2022.02-x86_64-aarch64-none-linux-gnu.tar.xz
tar xf gcc-arm-11.2-2022.02-x86_64-aarch64-none-linux-gnu.tar.xz
rm -f gcc-arm-11.2-2022.02-x86_64-aarch64-none-linux-gnu.tar.xz
export PATH=`pwd`/gcc-arm-11.2-2022.02-x86_64-aarch64-none-linux-gnu/bin:$PATH
export ARCH=arm64
export CROSS_COMPILE=aarch64-none-linux-gnu-

Building the Hardware Design

Use the following commands to build the hardware design:

cd $TOP_FOLDER
rm -rf ghrd-socfpga agilex_soc_devkit_ghrd
git clone -b QPDS23.4_REL_GSRD_PR https://github.com/altera-opensource/ghrd-socfpga
mv ghrd-socfpga/agilex_soc_devkit_ghrd .
rm -rf ghrd-socfpga
cd agilex_soc_devkit_ghrd
export HPS_ENABLE_SGMII=0
export ENABLE_PARTIAL_RECONFIGURATION=1
~/intelFPGA_pro/23.4/nios2eds/nios2_command_shell.sh make scrub_clean_all
~/intelFPGA_pro/23.4/nios2eds/nios2_command_shell.sh make generate_from_tcl
# fix issues in top level verilog file, if not already fixed
sed -i 's/fpga_reset_n,/fpga_reset_n/g' ghrd_agilex_top.v
~/intelFPGA_pro/23.4/nios2eds/nios2_command_shell.sh make all
unset HPS_ENABLE_SGMII
unset ENABLE_PARTIAL_RECONFIGURATION
unset QUARTUS_DEVICE
cd ..

The following files are created:

$TOP_FOLDER/agilex_soc_devkit_ghrd/output_files/ghrd_agfb014r24b2e2v.sof - FPGA configuration file, without HPS FSBL
$TOP_FOLDER/agilex_soc_devkit_ghrd/software/hps_debug/hps_debug.ihex - HPS Debug FSBL
$TOP_FOLDER/agilex_soc_devkit_ghrd/output_files/ghrd_agfb014r24b2e2v_hps_debug.sof - FPGA configuration file, with HPS Debug FSBL

Building Core RBF

Create the Core RBF file to be used in the rootfs created by Yocto by using the HPS Debug SOF built by the GHRD makefile:

cd $TOP_FOLDER
rm -f *jic* *rbf*
~/intelFPGA_pro/23.4/nios2eds/nios2_command_shell.sh \
  quartus_pfg -c agilex_soc_devkit_ghrd/output_files/ghrd_agfb014r24b2e2v_hps_debug.sof \
  ghrd_agfb014r24b2e2v.jic \
  -o device=MT25QU02G \
  -o flash_loader=AGFB014R24B2E2V \
  -o mode=ASX4 \
  -o hps=1
rm ghrd_agfb014r24b2e2v.hps.jic

The following files will be created:

$TOP_FOLDER/ghrd_agfb014r24b2e2v.core.rbf - HPS First configuration bitstream, phase 2: FPGA fabric

Note we are also creating an HPS JIC file, but we are discarding it, as it has the HPS Debug FSBL, while the final image needs to have the U-Boot SPL created by the Yocto recipes.

Setting Up Yocto Build System

1. First, make sure you have Yocto system requirements met: https://docs.yoctoproject.org/3.4.1/ref-manual/system-requirements.html#supported-linux-distributions.

The command to install the required packages on Ubuntu is:

sudo apt install gawk wget git diffstat unzip texinfo gcc build-essential chrpath \
socat cpio python3 python3-pip python3-pexpect xz-utils debianutils iputils-ping \
python3-git python3-jinja2 libegl1-mesa libsdl1.2-dev pylint3 xterm python3-subunit \
mesa-common-dev zstd liblz4-tool

2. Clone the Yocto script and prepare the build:

cd $TOP_FOLDER
rm -rf gsrd_socfpga
git clone -b nanbield https://github.com/altera-opensource/gsrd_socfpga
cd gsrd_socfpga
. agilex7_dk_si_agf014ea-gsrd-build.sh
build_setup

Note: Run the following commands to set up again the yocto build environments, if you closed the current window (for example when rebooting the Linux host) and want to resume the next steps:

cd $TOP_FOLDER/gsrd_socfpga
. ./poky/oe-init-build-env agilex-gsrd-rootfs/

Customize Yocto Build

1. Copy the rebuilt files to $WORKSPACE/meta-intel-fpga-refdes/recipes-bsp/ghrd/files using the following names, as expected by the yocto recipes:

agilex7_dk_si_agf014ea_gsrd_ghrd.core.rbf: not applicable
agilex7_dk_si_agf014ea_nand_ghrd.core.rbf: not applicable
agilex7_dk_si_agf014ea_pr_ghrd.core.rbf
agilex7_dk_si_agf014ea_pr_persona0.rbf
agilex7_dk_si_agf014ea_pr_persona1.rbf

In our case we just copy the core.ghrd file in the Yocto recipe location:

CORE_RBF=$WORKSPACE/meta-intel-fpga-refdes/recipes-bsp/ghrd/files/agilex7_dk_si_agf014ea_pr_ghrd.core.rbf
PER0_RBF=$WORKSPACE/meta-intel-fpga-refdes/recipes-bsp/ghrd/files/agilex7_dk_si_agf014ea_pr_persona0.rbf
PER1_RBF=$WORKSPACE/meta-intel-fpga-refdes/recipes-bsp/ghrd/files/agilex7_dk_si_agf014ea_pr_persona1.rbf
ln -s $TOP_FOLDER/ghrd_agfb014r24b2e2v.core.rbf $CORE_RBF
ln -s $TOP_FOLDER/agilex_soc_devkit_ghrd/output_files/ghrd_agfb014r24b2e2v.pr_partition_0.rbf $PER0_RBF
ln -s $TOP_FOLDER/agilex_soc_devkit_ghrd/output_files/alternate_persona.pr_partition_0.rbf $PER1_RBF

2. In the Yocto recipe $WORKSPACE/meta-intel-fpga-refdes/recipes-bsp/ghrd/hw-ref-design.bb modify the agilex_gsrd_code file location:

SRC_URI:agilex7_dk_si_agf014ea ?= "\
      ${GHRD_REPO}/agilex7_dk_si_agf014ea_gsrd_${ARM64_GHRD_CORE_RBF};name=agilex7_dk_si_agf014ea_gsrd_core \
      ${GHRD_REPO}/agilex7_dk_si_agf014ea_nand_${ARM64_GHRD_CORE_RBF};name=agilex7_dk_si_agf014ea_nand_core \
      ${GHRD_REPO}/agilex7_dk_si_agf014ea_pr_${ARM64_GHRD_CORE_RBF};name=agilex7_dk_si_agf014ea_pr_core \
      ${GHRD_REPO}/agilex7_dk_si_agf014ea_pr_persona0.rbf;name=agilex7_dk_si_agf014ea_pr_persona0 \
      ${GHRD_REPO}/agilex7_dk_si_agf014ea_pr_persona1.rbf;name=agilex7_dk_si_agf014ea_pr_persona1 \
      "

to look like this:

SRC_URI:agilex7_dk_si_agf014ea ?= "\
      ${GHRD_REPO}/agilex7_dk_si_agf014ea_gsrd_${ARM64_GHRD_CORE_RBF};name=agilex7_dk_si_agf014ea_gsrd_core \
      ${GHRD_REPO}/agilex7_dk_si_agf014ea_nand_${ARM64_GHRD_CORE_RBF};name=agilex7_dk_si_agf014ea_nand_core \
      file://agilex7_dk_si_agf014ea_pr_ghrd.core.rbf;sha256sum=xxxxxxxxxxx \
      file://agilex7_dk_si_agf014ea_pr_persona0.rbf;sha256sum=xxxxxxxxxxx \
      file://agilex7_dk_si_agf014ea_pr_persona1.rbf;sha256sum=xxxxxxxxxxx
      "

using the following commands:

CORE_SHA=$(sha256sum $CORE_RBF | cut -f1 -d" ")
PER0_SHA=$(sha256sum $PER0_RBF | cut -f1 -d" ")
PER1_SHA=$(sha256sum $PER1_RBF | cut -f1 -d" ")
OLD_CORE_URI="\${GHRD_REPO}\/agilex7_dk_si_agf014ea_pr_\${ARM64_GHRD_CORE_RBF};name=agilex7_dk_si_agf014ea_pr_core"
NEW_CORE_URI="file:\/\/agilex7_dk_si_agf014ea_pr_ghrd.core.rbf;sha256sum=$CORE_SHA"
OLD_PER0_URI="\${GHRD_REPO}\/agilex7_dk_si_agf014ea_pr_persona0.rbf;name=agilex7_dk_si_agf014ea_pr_persona0"
NEW_PER0_URI="file:\/\/agilex7_dk_si_agf014ea_pr_persona0.rbf;sha256sum=$PER0_SHA"
OLD_PER1_URI="\${GHRD_REPO}\/agilex7_dk_si_agf014ea_pr_persona1.rbf;name=agilex7_dk_si_agf014ea_pr_persona1"
NEW_PER1_URI="file:\/\/agilex7_dk_si_agf014ea_pr_persona1.rbf;sha256sum=$PER1_SHA"
RECIPE=$WORKSPACE/meta-intel-fpga-refdes/recipes-bsp/ghrd/hw-ref-design.bb
sed -i "s/$OLD_CORE_URI/$NEW_CORE_URI/g" $RECIPE
sed -i "s/$OLD_PER0_URI/$NEW_PER0_URI/g" $RECIPE
sed -i "s/$OLD_PER1_URI/$NEW_PER1_URI/g" $RECIPE

3. In the same Yocto recipe delete the old SHA256 checksum for the files:

SRC_URI[name=agilex7_dk_si_agf014ea_pr_core.sha256sum] = "69245470a36274f1f002cb275748664902d9262f577cae4bba92813cb48fdeaf"
SRC_URI[agilex7_dk_si_agf014ea_pr_persona0.sha256sum] = "6556cc83a8e8a38fb1e52945d91bd651466e9553f8e60c04df5e71ee36dc45f2"
SRC_URI[agilex7_dk_si_agf014ea_pr_persona1.sha256sum] = "8a0cdcb38aead468a62eb0cba68af05a4e242bd79a617f49176647d766b70b28"

by using the following commands:

sed -i '/name=agilex7_dk_si_agf014ea_pr_core\.sha256sum/d' $RECIPE
sed -i '/agilex7_dk_si_agf014ea_pr_persona0\.sha256sum/d' $RECIPE
sed -i '/agilex7_dk_si_agf014ea_pr_persona1\.sha256sum/d' $RECIPE

4. Optionally change the following files in $WORKSPACE/meta-intel-fpga-refdes/recipes-bsp/u-boot/files/:

uboot.txt - distroboot script
uboot_script.its - its file for creating FIT image from the above script

5. Optionally change the following file in $WORKSPACE/meta-intel-fpga-refdes/recipes-kernel/linux/linux-socfpga-lts:

fit_kernel_agilex7_dk_si_agf014ea.its - its file for creating the kernel.itb image, containing by default:
- Kernel
- Device trees for SD, NAND and PR board configurations
- Core RBF files for SD, NAND and PR board configurations
- Board configurations for SD, NAND and PR cases

Build Yocto

Build Yocto:

bitbake_image

Gather files:

package

Once the build is completed successfully, you will see the following two folders are created:

agilex7_dk_si_agf014ea-gsrd-rootfs: area used by OpenEmbedded build system for builds. Description of build directory structure - https://docs.yoctoproject.org/ref-manual/structure.html#the-build-directory-build
agilex7_dk_si_agf014ea-gsrd-images: the build script copies here relevant files built by Yocto from the agilex7_dk_si_agf014ea-gsrd-rootfs/tmp/deploy/images/agilex folder, but also other relevant files.

The two most relevant files created in the $TOP_FOLDER/gsrd_socfpga/agilex7_dk_si_agf014ea-gsrd-images folder are:

File	Description
sdimage.tar.gz	SD Card Image
u-boot-agilex-socdk-gsrd-atf/u-boot-spl-dtb.hex	U-Boot SPL Hex file

Building QSPI Flash Image

The QSPI image will contain the FPGA configuration data and the HPS FSBL and it can be built using the following command:

cd $TOP_FOLDER
rm -f *jic* *rbf*
~/intelFPGA_pro/23.4/nios2eds/nios2_command_shell.sh \
  quartus_pfg -c agilex_soc_devkit_ghrd/output_files/ghrd_agfb014r24b2e2v.sof \
  ghrd_agfb014r24b2e2v.jic \
  -o hps_path=gsrd_socfpga/agilex7_dk_si_agf014ea-gsrd-images/u-boot-agilex7-socdk-gsrd-atf/u-boot-spl-dtb.hex \
  -o device=MT25QU02G \
  -o flash_loader=AGFB014R24B2E2V \
  -o mode=ASX4 \
  -o hps=1

The following files will be created:

$TOP_FOLDER/ghrd_agfb014r24b2e2v.hps.jic - Flash image for HPS First configuration bitstream, phase 1: HPS and DDR
$TOP_FOLDER/ghrd_agfb014r24b2e2v.core.rbf - HPS First configuration bitstream, phase 2: FPGA fabric, discarded, as we already have it on the SD card

PR Files

The files on the Linux rootfs used for running the PR scenarios are shown below:

File	Description
/sbin/dtbt	Tool used for managing the overlays. Available at https://github.com/altera-opensource/dtbt
/boot/devicetree/agilex7_pr_fpga_static_region.dtbo	overlay for the static region, needs to be applied before persona overlays
/boot/devicetree/agilex7_pr_persona0.dtbo	overlay for persona0
/boot/devicetree/agilex7_pr_persona0.dtbo	overlay for persona1
/lib/firmware/persona0.rbf	bitstream used by persona0 overlay
/lib/firmware/persona1.rbf	bitstream used by persona1 overlay

The DTS files for the overlays are available at https://github.com/altera-opensource/meta-intel-fpga-refdes/blob/nanbield/recipes-bsp/device-tree/files/:

agilex7_pr_fpga_static_region.dts
agilex7_pr_persona0.dts
agilex7_pr_persona1.dts

Running PR Scenarios

1. Boot Linux

2. Add the overlay for the static region:

root@agilex7dksiagf014ea:~# dtbt -a agilex7_pr_fpga_static_region.dtbo -p /boot/devicetree
Set dtbo search path to /boot/devicetree
[  292.932872] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /soc/base_fpga_region/ranges
Applying dtbo: agilex_pr_fpga_static_region.dtbo
[  292.944184] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /soc/base_fpga_region/external-fpga-config
[  292.960109] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /soc/base_fpga_region/clocks
[  292.970529] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /soc/base_fpga_region/clock-names
[  292.981470] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/clk_0
[  292.991034] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/freeze_controller_0
[  293.007735] of-fpga-region soc:base_fpga_region:fpga_pr_region0: FPGA Region probed
[  293.028076] altera_freeze_br f9000450.freeze_controller: fpga bridge [freeze] registered

3. Add the overlay for persona0:

root@agilex7dksiagf014ea:~# dtbt -a agilex7_pr_persona0.dtbo -p /boot/devicetree
Set dtbo search path to /boot/devicetree
[  398.171799] fpga_manager fpga0: writing persona0.rbf to Stratix10 SOC FPGA Manager
Applying dtbo: agilex_pr_persona0.dtbo
[  398.321356] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/pr_region_0_pr_clk_100
[  398.332459] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/pr_region_0_pr_sysid_qsys_0

4. Locate the sysid and display the associated id:

root@agilex7dksiagf014ea:~# find / -name sysid
/sys/devices/platform/soc/soc:base_fpga_region/soc:base_fpga_region:fpga_pr_region0/f9000800.sysid/sysid
root@agilex7dksiagf014ea:~# cat /sys/devices/platform/soc/soc:base_fpga_region/soc:base_fpga_region:fpga_pr_region0/f9000800.sysid/sysid/id | xargs printf "0x%08x\n"
0xcafeface

5. List the applied overlays:

root@agilex7dksiagf014ea:~# dtbt -l
2 agilex_pr_persona0.dtbo applied /sys/kernel/config/device-tree/overlays/2-agilex_pr_persona0.dtbo
1 agilex_pr_fpga_static_region.dtbo applied /sys/kernel/config/device-tree/overlays/1-agilex_pr_fpga_static_region.dtbo

6. Remove persona0 overlay:

root@agilex7dksiagf014ea:~# dtbt -r agilex7_pr_persona0.dtbo -p /boot/devicetree 
Set dtbo search path to /boot/devicetree
Removing dtbo: 2-agilex_pr_persona0.dtbo

7. Add the persona1 overlay:

root@agilex7dksiagf014ea:~# dtbt -a agilex7_pr_persona1.dtbo -p /boot/devicetree 
Set dtbo search path to /boot/devicetree
[  531.975623] fpga_manager fpga0: writing persona1.rbf to Stratix10 SOC FPGA Manager
Applying dtbo: agilex_pr_persona1.dtbo
[  532.124433] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/pr_region_0_pr_clk_100
[  532.135530] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/pr_region_0_pr_sysid_qsys_0

8. Locate the sysid and display the associated id:

root@agilex7dksiagf014ea:~# find / -name sysid
/sys/devices/platform/soc/soc:base_fpga_region/soc:base_fpga_region:fpga_pr_region0/f9000900.sysid/sysid
root@agilex7dksiagf014ea:~# cat /sys/devices/platform/soc/soc:base_fpga_region/soc:base_fpga_region:fpga_pr_region0/f9000900.sysid/sysid/id | xargs printf "0x%08x\n"
0xfacecafe

9. Remove persona1:

root@agilex7dksiagf014ea:~# dtbt -r agilex7_pr_persona1.dtbo -p /boot/devicetree
Set dtbo search path to /boot/devicetree
Removing dtbo: 2-agilex_pr_persona1.dtbo

10. List the applied overlays:

root@agilex7dksiagf014ea:~# dtbt -l
1 agilex_pr_fpga_static_region.dtbo applied /sys/kernel/config/device-tree/overlays/1-agilex_pr_fpga_static_region.dtbo

Building the GSRD for the DK-SI-AGF014EB Version

No binaries are provided for the DK-SI-AGF014EB version, but they can be built using the DK-SI-AGF014EA instructions presented in the previous sections, and only changing the hardware design.

This section below shows how to build the binaries for booting from SD card, but a similar change can be done for the remaining scenarions: boot from QSPI, boot from NAND and Partial Reconfiguration.

Build Flow

The following diagram illustrates the full build flow for the GSRD based on source code from GitHub.

Setting up Environment

Create a top folder for this example, as the rest of the commands assume this location:

sudo rm -rf agilex_gsrd_linear
mkdir agilex_gsrd_linear
cd agilex_gsrd_linear
export TOP_FOLDER=$(pwd)

Download the compiler toolchain, add it to the PATH variable, to be used by the GHRD makefile to build the HPS Debug FSBL:

cd $TOP_FOLDER
wget https://developer.arm.com/-/media/Files/downloads/gnu/11.2-2022.02/binrel/\
gcc-arm-11.2-2022.02-x86_64-aarch64-none-linux-gnu.tar.xz
tar xf gcc-arm-11.2-2022.02-x86_64-aarch64-none-linux-gnu.tar.xz
rm -f gcc-arm-11.2-2022.02-x86_64-aarch64-none-linux-gnu.tar.xz
export PATH=`pwd`/gcc-arm-11.2-2022.02-x86_64-aarch64-none-linux-gnu/bin:$PATH
export ARCH=arm64
export CROSS_COMPILE=aarch64-none-linux-gnu-

Updating and Building the Hardware Design

Use the following commands to build the hardware design:

cd $TOP_FOLDER
rm -rf ghrd-socfpga agilex_soc_devkit_ghrd
git clone -b QPDS23.4_REL_GSRD_PR https://github.com/altera-opensource/ghrd-socfpga
mv ghrd-socfpga/agilex_soc_devkit_ghrd .
rm -rf ghrd-socfpga
cd agilex_soc_devkit_ghrd
~/intelFPGA_pro/23.4/nios2eds/nios2_command_shell.sh make scrub_clean_all
export BOARD_PWRMGT=linear
~/intelFPGA_pro/23.4/nios2eds/nios2_command_shell.sh make generate_from_tcl
# fix issues in top level verilog file, if not already fixed
sed -i 's/fpga_reset_n,/fpga_reset_n/g' ghrd_agilex_top.v
~/intelFPGA_pro/23.4/nios2eds/nios2_command_shell.sh make all
cd ..

The following files are created:

$TOP_FOLDER/agilex_soc_devkit_ghrd/output_files/ghrd_agfb014r24b2e2v.sof - FPGA configuration file, without HPS FSBL
$TOP_FOLDER/agilex_soc_devkit_ghrd/software/hps_debug/hps_debug.ihex - HPS Debug FSBL
$TOP_FOLDER/agilex_soc_devkit_ghrd/output_files/ghrd_agfb014r24b2e2v_hps_debug.sof - FPGA configuration file, with HPS Debug FSBL

Building Core RBF

Create the Core RBF file to be used in the rootfs created by Yocto by using the HPS Debug SOF built by the GHRD makefile:

cd $TOP_FOLDER
rm -f *jic* *rbf*
~/intelFPGA_pro/23.4/nios2eds/nios2_command_shell.sh \
  quartus_pfg -c agilex_soc_devkit_ghrd/output_files/ghrd_agfb014r24b2e2v_hps_debug.sof \
  ghrd_agfb014r24b2e2v.jic \
  -o device=MT25QU02G \
  -o flash_loader=AGFB014R24B2E2V \
  -o mode=ASX4 \
  -o hps=1
rm ghrd_agfb014r24b2e2v.hps.jic

The following files will be created:

$TOP_FOLDER/ghrd_agfb014r24b2e2v.core.rbf - HPS First configuration bitstream, phase 2: FPGA fabric

Note we are also creating an HPS JIC file, but we are discarding it, as it has the HPS Debug FSBL, while the final image needs to have the U-Boot SPL created by the Yocto recipes.

Setting Up Yocto Build System

1. First, make sure you have Yocto system requirements met: https://docs.yoctoproject.org/3.4.1/ref-manual/system-requirements.html#supported-linux-distributions.

The command to install the required packages on Ubuntu 20.04 is:

sudo apt-get update
sudo apt-get upgrade
sudo apt-get install openssh-server mc libgmp3-dev libmpc-dev gawk wget git diffstat unzip texinfo gcc \
build-essential chrpath socat cpio python3 python3-pip python3-pexpect xz-utils debianutils iputils-ping \
python3-git python3-jinja2 libegl1-mesa libsdl1.2-dev pylint3 xterm python3-subunit mesa-common-dev zstd \
liblz4-tool git fakeroot build-essential ncurses-dev xz-utils libssl-dev bc flex libelf-dev bison xinetd \
tftpd tftp nfs-kernel-server libncurses5 libc6-i386 libstdc++6:i386 libgcc++1:i386 lib32z1 \
device-tree-compiler curl mtd-utils u-boot-tools net-tools swig -y

On Ubuntu 20.04 you will also need to point the /bin/sh to /bin/bash, as the default is a link to /bin/dash:

sudo ln -sf /bin/bash /bin/sh

2. Clone the Yocto script and prepare the build:

cd $TOP_FOLDER
rm -rf gsrd_socfpga
git clone -b nanbield https://github.com/altera-opensource/gsrd_socfpga
cd gsrd_socfpga
. agilex7_dk_si_agf014eb-gsrd-build.sh
build_setup

Note: Run the following commands to set up again the yocto build environments, if you closed the current window (for example when rebooting the Linux host) and want to resume the next steps:

cd $TOP_FOLDER/gsrd_socfpga
. ./poky/oe-init-build-env agilex-gsrd-rootfs/

Customize Yocto Build

1. Copy the rebuilt files to $WORKSPACE/meta-intel-fpga-refdes/recipes-bsp/ghrd/files using the following names, as expected by the yocto recipes:

agilex7_dk_si_agf014eb_gsrd_ghrd.core.rbf

We copy the core.ghrd file in the Yocto recipe location:

CORE_RBF=$WORKSPACE/meta-intel-fpga-refdes/recipes-bsp/ghrd/files/agilex7_dk_si_agf014eb_gsrd_ghrd.core.rbf
ln -s $TOP_FOLDER/ghrd_agfb014r24b2e2v.core.rbf $CORE_RBF

2. In the Yocto recipe $WORKSPACE/meta-intel-fpga-refdes/recipes-bsp/ghrd/hw-ref-design.bb modify the agilex_gsrd_code file location:

SRC_URI:agilex7_dk_si_agf014eb ?= "\
      ${GHRD_REPO}/agilex7_dk_si_agf014eb_gsrd_${ARM64_GHRD_CORE_RBF};name=agilex7_dk_si_agf014eb_gsrd_core \
      "

to look like this:

SRC_URI:agilex7_dk_si_agf014eb ?= "\
    file://agilex7_dk_si_agf014eb_gsrd_ghrd.core.rbf;sha256sum=xxxxxxxxx \
    "

using the following commands:

OLD_URI="\${GHRD_REPO}\/agilex7_dk_si_agf014eb_gsrd_\${ARM64_GHRD_CORE_RBF};name=agilex7_dk_si_agf014eb_gsrd_core"
CORE_SHA=$(sha256sum $CORE_RBF | cut -f1 -d" ")
NEW_URI="file:\/\/agilex7_dk_si_agf014eb_gsrd_ghrd.core.rbf;sha256sum=$CORE_SHA"
sed -i "s/$OLD_URI/$NEW_URI/g" $WORKSPACE/meta-intel-fpga-refdes/recipes-bsp/ghrd/hw-ref-design.bb

3. In the same Yocto recipe delete the old SHA256 checksum for the file:

SRC_URI[agilex7_dk_si_agf014eb_gsrd_core.sha256sum] = "5d633ee561d5cc8c22b51211a144654fdc0be47ee14b07ac134074cbff84eb8b"

by using the following commands:

sed -i "/agilex7_dk_si_agf014eb_gsrd_core\.sha256sum/d" $WORKSPACE/meta-intel-fpga-refdes/recipes-bsp/ghrd/hw-ref-design.bb

4. Optionally change the following files in $WORKSPACE/meta-intel-fpga-refdes/recipes-bsp/u-boot/files/:

uboot.txt - distroboot script
uboot_script.its - its file for creating FIT image from the above script

5. Optionally change the following file in $WORKSPACE/meta-intel-fpga-refdes/recipes-kernel/linux/linux-socfpga-lts:

fit_kernel_agilex.its - its file for creating the kernel.itb image, containing by default:
- Kernel
- Device trees for SD, NAND and PR board configurations
- Core RBF files for SD, NAND and PR board configurations
- Board configurations for SD, NAND and PR cases

Build Yocto

Build Yocto:

bitbake_image

Gather files:

package

Once the build is completed successfully, you will see the following two folders are created:

agilex7_dk_si_agf014eb-gsrd-rootfs: area used by OpenEmbedded build system for builds. Description of build directory structure - https://docs.yoctoproject.org/ref-manual/structure.html#the-build-directory-build
agilex7_dk_si_agf014eb-gsrd-images: the build script copies here relevant files built by Yocto from the agilex7_dk_si_agf014eb-gsrd-rootfs/tmp/deploy/images/agilex folder, but also other relevant files.

The two most relevant files created in the $TOP_FOLDER/gsrd_socfpga/agilex7_dk_si_agf014eb-gsrd-images folder are:

File	Description
sdimage.tar.gz	SD Card Image
u-boot-agilex7-socdk-gsrd-atf/u-boot-spl-dtb.hex	U-Boot SPL Hex file

Building QSPI Flash Image

The QSPI image will contain the FPGA configuration data and the HPS FSBL and it can be built using the following command:

cd $TOP_FOLDER
rm -f *jic* *rbf*
~/intelFPGA_pro/23.4/nios2eds/nios2_command_shell.sh \
  quartus_pfg -c agilex_soc_devkit_ghrd/output_files/ghrd_agfb014r24b2e2v.sof \
  ghrd_agfb014r24b2e2v.jic \
  -o hps_path=gsrd_socfpga/agilex7_dk_si_agf014eb-gsrd-images/u-boot-agilex7-socdk-gsrd-atf/u-boot-spl-dtb.hex \
  -o device=MT25QU02G \
  -o flash_loader=AGFB014R24B2E2V \
  -o mode=ASX4 \
  -o hps=1

The following files will be created:

$TOP_FOLDER/ghrd_agfb014r24b2e2v.hps.jic - Flash image for HPS First configuration bitstream, phase 1: HPS and DDR
$TOP_FOLDER/ghrd.core.rbf - HPS First configuration bitstream, phase 2: FPGA fabric, discarded, as we already have it on the SD card

Disabling Unused Flash Devices in U-Boot for Faster Booting

This release of the GSRD uses the same U-Boot binaries to boot from all supported flash devices: SD, QSPI and NAND.

U-Boot will try to initialize all the flash devices, adding to the boot time. You can disable the unused flash devices by doing the following:

Change U-Boot defconfig to remove support for the flash
Change U-Boot device tree to disable the flash, and not try to boot from it.

The following shows for example how to disable NAND support, by adding another Yocto layer containing a new U-Boot patch:

1. Set up Yocto build using the standard instructions:

cd $TOP_FOLDER
rm -rf gsrd_socfpga
git clone -b nanbield https://github.com/altera-opensource/gsrd_socfpga
cd gsrd_socfpga
. agilex7_dk_si_agf014ea-gsrd-build.sh
build_setup

2. Customize Yocto build as necessary to use the recompiled GHRD files for example, using the standard instructions.

3. Use devtool to modify U-Boot to disable NAND support:

cd $TOP_FOLDER/gsrd_socfpga/agilex-gsrd-rootfs/
devtool modify virtual/bootloader
cd workspace/sources/u-boot-socfpga
sed -i 's/u-boot,spl-boot-order.*/u-boot\,spl-boot-order = \&mmc;/g' arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi
sed -i '/&nand {/!b;n;c\\tstatus = "disabled";' arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi
sed -i '/NAND/d' configs/socfpga_agilex_defconfig
git commit -a -m "remove nand support"

4. Create new layer and add the U-Boot patch to it:

bitbake-layers create-layer $TOP_FOLDER/gsrd_socfpga/meta-modified-project
devtool update-recipe -a $TOP_FOLDER/gsrd_socfpga/meta-modified-project u-boot-socfpga
cd $TOP_FOLDER/gsrd_socfpga/agilex-gsrd-rootfs/
bitbake-layers add-layer $TOP_FOLDER/gsrd_socfpga/meta-modified-project

5. Remove the temporary layer and workspace created by devtool:

bitbake-layers remove-layer $TOP_FOLDER/gsrd_socfpga/agilex-gsrd-rootfs/workspace
rm -rf $TOP_FOLDER/gsrd_socfpga/agilex-gsrd-rootfs/workspace

6. Buid the Yocto recipes as usual:

bitbake_image
package

7. Build the rest of the files, as usual.

For reference, the U-Boot patch created by the above instructions looks like this:

From ff5d2cc480d29ee5673e7e2a4ce146be47737d9c Mon Sep 17 00:00:00 2001
From: Radu Bacrau <radu.bacrau@intel.com>
Date: Wed, 9 Mar 2022 09:20:23 -0600
Subject: [PATCH] remove nand support

---
 arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi | 4 ++--
 configs/socfpga_agilex_defconfig              | 9 ---------
 2 files changed, 2 insertions(+), 11 deletions(-)

diff --git a/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi
index b12b460214..8be8a9ec0c 100644
--- a/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi
@@ -10,7 +10,7 @@
 /{
 	chosen {
 		stdout-path = "serial0:115200n8";
-		u-boot,spl-boot-order = &mmc,&flash0,&nand;
+		u-boot,spl-boot-order = &mmc;
 	};
 
 	aliases {
@@ -46,7 +46,7 @@
 };
 
 &nand {
-	status = "okay";
+	status = "disabled";
 	nand-bus-width = <16>;
 	u-boot,dm-pre-reloc;
 };
diff --git a/configs/socfpga_agilex_defconfig b/configs/socfpga_agilex_defconfig
index b4f4251bf2..f221619320 100644
--- a/configs/socfpga_agilex_defconfig
+++ b/configs/socfpga_agilex_defconfig
@@ -20,7 +20,6 @@ CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_SPL_LOAD_FIT_ADDRESS=0x02000000
 # CONFIG_USE_SPL_FIT_GENERATOR is not set
-CONFIG_NAND_BOOT=y
 CONFIG_QSPI_BOOT=y
 CONFIG_BOOTDELAY=5
 CONFIG_USE_BOOTARGS=y
@@ -28,7 +27,6 @@ CONFIG_BOOTARGS="earlycon panic=-1"
 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
 CONFIG_SPL_CRC32_SUPPORT=y
 CONFIG_SPL_MTD_SUPPORT=y
-CONFIG_SPL_NAND_SUPPORT=y
 CONFIG_SPL_CACHE=y
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SPL_ATF=y
@@ -40,8 +38,6 @@ CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_MTD=y
-CONFIG_CMD_NAND_TRIMFFS=y
-CONFIG_CMD_NAND_LOCK_UNLOCK=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_CACHE=y
@@ -73,11 +69,6 @@ CONFIG_MISC=y
 CONFIG_MMC_DW=y
 CONFIG_MTD=y
 CONFIG_DM_MTD=y
-CONFIG_NAND_DENALI_DT=y
-CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
-CONFIG_SYS_NAND_U_BOOT_OFFS=0x0
-CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND=0x100000
-CONFIG_SPL_NAND_FRAMEWORK=y
 CONFIG_SF_DEFAULT_MODE=0x2003
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y

Reconfiguring Core Fabric from U-Boot

The GSRD configures the FPGA core fabric only once, from U-Boot, by using the bootm command.

Important : If the FPGA fabric is already configured and bridges are enabled, you must call the bridge disable command from U-Boot before issuing the bootm or fppga load commands to reconfigure the fabric. Only do this if you are using an arm-trusted-firmware version more recent than the following:

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GSRD for Agilex 7 F-Series Transceiver-SoC DevKit (P-Tile and E-Tile) Golden System Reference Design for DK-SI-AGF014EA

Overview

Prerequisites

Release Contents

Intel FPGA HPS Embedded Software Release Notes

Latest Binaries Release Content

Boot from SD Card Binaries

Boot from NAND Binaries

Boot from QSPI Binaries

Latest Source Code Release Contents - Branches and Commit IDs

GHRD Overview

Cortex-A53 MPU Address Maps

HPS-to-FPGA Address Map

Lightweight HPS-to-FPGA Address Map

JTAG Master Address Map

Interrupt Routing

Typical HPS Boot Flow

Running GSRD with Pre-Built Binaries for the DK-SI-AGF014EA Version

Booting Linux Using Precompiled Binaries

Configuring Board

Writing JIC Image to QSPI Flash

Creating SD Card

Creating SD Card on Linux

Creating SD Card on Windows

Configuring Serial Connection

Booting Linux

Running Sample Linux Applications

Prerequisites

Display Hello World Message

Exercise Soft PIO Driver for LED Control

Register Interrupts and Call Interrupt Service Routine

System Check Application

Connecting to Board Web Server and SSH Client

Connect to Web Server

Connect Using SSH

Building the GSRD for the DK-SI-AGF014EA Version

Build Flow

Setting up Environment

Building the Hardware Design

Building Core RBF

Setting Up Yocto Build System

Customize Yocto Build

Build Yocto

Building QSPI Flash Image

Booting from QSPI for the DK-SI-AGF014EA Version

QSPI Flash Layout

Creating the QSPI Flash Image

Creating the Programming File Generator File

Writing the QSPI Flash Image

Booting Linux

Booting From NAND for the DK-SI-AGF014EA Version

NAND Flash Layout

Setting up Environment

Building the Hardware Design

Building Core RBF

Setting Up Yocto Build System

Customize Yocto Build

Build Yocto

Building QSPI Flash Image

Building NAND Binaries

Write NAND Binaries

Write Binaries to NAND

Write QSPI Image

Boot Linux

Partial Reconfiguration for the DK-SI-AGF014EA Version

Reference Information

Hardware Design

Setting up Environment

Building the Hardware Design

Building Core RBF

Setting Up Yocto Build System

Customize Yocto Build

Build Yocto

Building QSPI Flash Image

PR Files

Running PR Scenarios

Building the GSRD for the DK-SI-AGF014EB Version

Build Flow

Setting up Environment

Updating and Building the Hardware Design

GSRD for Agilex 7 F-Series Transceiver-SoC DevKit (P-Tile and E-Tile)
Golden System Reference Design for DK-SI-AGF014EA