Overview

This page presents the Golden System Reference Design for the Intel Agilex® 7 FPGA M-Series Development Kit - HBM2e Edition (3x F-Tile & 1x R-Tile). The GSRD demonstrates the following:

• HPS side
  • Linux, booted by U-Boot and ATF
  • Board web server
  • Sample applications
    • Hello world
    • System check application

Prerequisites

The following are required in order to be able to fully exercise the GSRD:

• Intel Agilex® 7 FPGA M-Series Development Kit - HBM2e Edition (3x F-Tile & 1x R-Tile), ordering code DK-DEV-AGM039FES
  • SD/MMC HPS Daughtercard
  • Mini USB cable for serial output
  • Micro USB cable for on-board Intel FPGA Download Cable II
• Micro SD card (4GB or greater)
• Host PC with
  • Linux - Ubuntu 22.04LTS was used to create this page, other versions and distributions may work too
  • Serial terminal (for example Minicom on Linux and TeraTerm or PuTTY on Windows)
  • Micro SD card slot or Micro SD card writer/reader
  • Intel Quartus Prime Pro Edition
    • v24.1 for the prebuilt binaries
    • v24.1 for rebuilding the binaries
• Local Ethernet network, with DHCP server (will be used to provide IP address to the board)

Note that the U-Boot and Linux compilation, Yocto compilation and creating the SD card image require a Linux host PC. The rest of the operations can be performed on either a Windows or Linux host PC.

Release Notes

The Intel FPGA HPS Embedded Software release notes can be accessed from the following link: https://www.rocketboards.org/foswiki/Documentation/IntelFPGAHPSEmbeddedSoftwareRelease

Binary Release Contents

The binary release files are accessible at https://releases.rocketboards.org/2024.04/gsrd/agilex7_dk_dev_agm039fes_gsrd/.

The source code is also included on the SD card in the Linux rootfs path /home/root:

File	Description
linux-socfpga-v6.1.68-lts-src.tar.gz	Source code for Linux kernel
u-boot-socfpga-v2023.10-src.tar.gz	Source code for U-Boot
arm-trusted-firmware-v2.10-src.tar.gz	Source code for Arm Trusted Firmware

Before downloading the hardware design please read the agreement in the link https://www.intel.com/content/www/us/en/programmable/downloads/software/license/lic-prog_lic.html

Source Code Release

Quartus Prime Pro v24.1 and the following software component versions are used to build the GSRD:

Component	Location	Branch	Commit ID/Tag
GHRD	https://github.com/altera-opensource/ghrd-socfpga	master	QPDS24.1_REL_GSRD_PR
Linux	https://github.com/altera-opensource/linux-socfpga	socfpga-6.1.68-lts	QPDS24.1_REL_GSRD_PR
Arm Trusted Firmware	https://github.com/arm-trusted-firmware	socfpga_v2.10.0	QPDS24.1_REL_GSRD_PR
U-Boot	https://github.com/altera-opensource/u-boot-socfpga	socfpga_v2023.10	QPDS24.1_REL_GSRD_PR
Yocto Project	https://git.yoctoproject.org/poky	nanbield	latest
Yocto Project: meta-intel-fpga	https://git.yoctoproject.org/meta-intel-fpga	nanbield	latest
Yocto Project: meta-intel-fpga-refdes	https://github.com/altera-opensource/meta-intel-fpga-refdes	nanbield	QPDS24.1_REL_GSRD_PR

Development Kit

The Agilex 7 M-Series HBM Development Kit is shown below:

Refer to the following for more information about the Development Kit:

• Installer Package
• Board User Guide

Running GSRD with Pre-Built Binaries

Booting Linux

1. Connect the following cables to the board:

• Power: from board to power supply
• HPS UART Console: from vertical mini USB connector on the HPS daughtercard to host PC
• JTAG: from micro USB cable on edge of the board to host PC

2. Download, extract and write to SD card the following SD card image: https://releases.rocketboards.org/2024.04/gsrd/agilex7_dk_dev_agm039fes_gsrd/sdimage.tar.gz. Then insert SD card into the HPS OOBE Daughtercard socket.

3. Configure board to the default settings, making sure set S24 dipswitch to OFF-OFF-OFF-ON, to select MSEL=JTAG, so that board does not configure on power up.

4. Power up the board

5. Download the HPS RBF file and configure the HPS RBF file over JTAG:

wget https://releases.rocketboards.org/2024.04/gsrd/agilex7_dk_dev_agm039fes_gsrd/ghrd.hps.rbf
quartus_pgm -c 1 -m jtag -o "p;ghrd_agmf039r47a1e2vr0.hps.rbf"

6. Linux will boot, use 'root' as username to log in, no password will be required:

U-Boot SPL 2023.10 (Mar 21 2024 - 07:41:59 +0000)
Reset state: Cold
MPU          1200000 kHz
L4 Main	      400000 kHz
L4 sys free   100000 kHz
L4 MP         200000 kHz
L4 SP         100000 kHz
SDMMC          50000 kHz
DDR: Populating DDR handoff
populate_ddr_handoff: MPFE-EMIF is in multichannel mode
populate_ddr_handoff: Memory type is DDR
populate_ddr_handoff: IO96B 0xf8400000 CSR enabled
populate_ddr_handoff: returned num_instance 0x1
DDR: Address MPFE 0xf8020000
is_ddr_init_hang: 0x8000000
DDR: SDRAM init in progress …
init_mem_cal: Initial DDR calibration IO96B_0 succeed
DDR: MPFE configuration in progress …
config_mpfe_sideband_mgr: F2SDRAM_SIDEBAND_FLAGOUTSTATUS0: 0x110
config_mpfe_sideband_mgr: Multichannel bit is set
DDR: MPFE configuration completed
DDR: Waiting for NOCPLL locked …
DDR: NOCPLL locked
DDR: Checking calibration...
io96b_mb_init: num_instance 1
io96b_mb_init: get memory interface IO96B 0
io96b_mb_req: Write 0x10001 to IOSSM_CMD_REQ_OFFSET 0xf840043c
io96b_mb_req: CMD_RESPONSE_STATUS 0xf840045c: 0x10001
io96b_mb_req: IOSSM_CMD_RESPONSE_DATA_0_OFFSET 0xf8400458: 0x20000000
io96b_mb_req: IOSSM_CMD_RESPONSE_DATA_1_OFFSET 0xf8400454: 0x0
io96b_mb_req: CMD_RESPONSE_STATUS 0xf840045c: 0x10001
io96b_mb_req: CMD_RESPONSE_READY 0xf840045c: 0x10000
io96b_mb_init: get response from memory interface IO96B 0
io96b_mb_init: IO96B 0: num_mem_interface: 0x1
io96b_mb_init: IO96B 0: ip_type_ret: 0x1
io96b_mb_init: IO96B 0: instance_id_ret: 0x0
DDR: Calibration success
io96b_mb_req: Write 0x20020002 to IOSSM_CMD_REQ_OFFSET 0xf840043c
io96b_mb_req: CMD_RESPONSE_STATUS 0xf840045c: 0x10001
io96b_mb_req: CMD_RESPONSE_STATUS 0xf840045c: 0x10001
io96b_mb_req: CMD_RESPONSE_READY 0xf840045c: 0x10000
io96b_mb_req: Write 0x20020004 to IOSSM_CMD_REQ_OFFSET 0xf840043c
io96b_mb_req: CMD_RESPONSE_STATUS 0xf840045c: 0x1
io96b_mb_req: IOSSM_CMD_RESPONSE_DATA_0_OFFSET 0xf8400458: 0x120
io96b_mb_req: IOSSM_CMD_RESPONSE_DATA_1_OFFSET 0xf8400454: 0x20
io96b_mb_req: CMD_RESPONSE_STATUS 0xf840045c: 0x1
io96b_mb_req: CMD_RESPONSE_READY 0xf840045c: 0x0
DDR: Warning: DRAM size from device tree (2048 MiB)
 mismatch with hardware (4096 MiB).
DDR5: 2048 MiB
io96b_mb_req: Write 0x20040102 to IOSSM_CMD_REQ_OFFSET 0xf840043c
io96b_mb_req: CMD_RESPONSE_STATUS 0xf840045c: 0x1
io96b_mb_req: CMD_RESPONSE_STATUS 0xf840045c: 0x1
io96b_mb_req: CMD_RESPONSE_READY 0xf840045c: 0x0
ecc_enable_status: ECC enable status: 0
DDR5: size check success
DDR5: firewall init success
DDR5 init success
WDT:   Started watchdog@ffd00200 with servicing every 1000ms (10s timeout)
denali-nand-dt nand@ffb90000: timeout while waiting for irq 0x2000
denali-nand-dt nand@ffb90000: reset not completed.
Trying to boot from MMC1
## Checking hash(es) for config board-0 … OK
## Checking hash(es) for Image atf … crc32+ OK
## Checking hash(es) for Image uboot … crc32+ OK
## Checking hash(es) for Image fdt-0 … crc32+ OK
NOTICE:  BL31: v2.10.0	(release):QPDS24.1_REL_GSRD_PR
NOTICE:  BL31: Built : 08:52:03, Mar 21 2024

U-Boot 2023.10 (Mar 21 2024 - 07:41:59 +0000)socfpga_agilex7

CPU:   Intel FPGA SoCFPGA Platform (ARMv8 64bit Cortex-A53)
Model: SoCFPGA Agilex7-M SoCDK
DRAM:  2 GiB
Core:  27 devices, 22 uclasses, devicetree: separate
WDT:   Started watchdog@ffd00200 with servicing every 1000ms (10s timeout)
NAND:  denali-nand-dt nand@ffb90000: timeout while waiting for irq 0x2000
denali-nand-dt nand@ffb90000: reset not completed.
Failed to initialize Denali NAND controller. (error -5)
0 MiB
MMC:   dwmmc0@ff808000: 0
Loading Environment from FAT... Unable to read "uboot.env" from mmc0:1...
Loading Environment from UBI... denali-nand-dt nand@ffb90000: timeout while waiting for irq 0x2000
denali-nand-dt nand@ffb90000: reset not completed.
Could not find a valid device for ffb90000.nand.0
Partition root not found!

** Cannot find mtd partition "root"
In:    serial0@ffc02000
Out:   serial0@ffc02000
Err:   serial0@ffc02000
Net:   
Warning: ethernet@ff800000 (eth0) using random MAC address - de:31:30:39:b5:20
eth0: ethernet@ff800000
Hit any key to stop autoboot:  5  4  3  2  1  0 
switch to partitions #0, OK
mmc0 is current device
Scanning mmc 0:1...
Found U-Boot script /boot.scr.uimg
2411 bytes read in 4 ms (587.9 KiB/s)
## Executing script at 05ff0000
crc32+ Trying to boot Linux from device mmc0
Found kernel in mmc0
12779603 bytes read in 608 ms (20 MiB/s)
## Loading kernel from FIT Image at 02000000 …
   Using 'board-4' configuration
   Verifying Hash Integrity … OK
   Trying 'kernel' kernel subimage
     Description:  Linux Kernel
     Type:         Kernel Image
     Compression:  lzma compressed
     Data Start:   0x020000dc
     Data Size:    9515437 Bytes = 9.1 MiB
     Architecture: AArch64
     OS:           Linux
     Load Address: 0x06000000
     Entry Point:  0x06000000
     Hash algo:    crc32
     Hash value:   b405983b
   Verifying Hash Integrity … crc32+ OK
## Loading fdt from FIT Image at 02000000 …
   Using 'board-4' configuration
   Verifying Hash Integrity … OK
   Trying 'fdt-4' fdt subimage
     Description:  socfpga_socdk_combined
     Type:         Flat Device Tree
     Compression:  uncompressed
     Data Start:   0x0291ab74
     Data Size:    32237 Bytes = 31.5 KiB
     Architecture: AArch64
     Hash algo:    crc32
     Hash value:   ca3cc1e7
   Verifying Hash Integrity … crc32+ OK
   Booting using the fdt blob at 0x291ab74
Working FDT set to 291ab74
## Loading fpga from FIT Image at 02000000 …
   Trying 'fpga-4' fpga subimage
     Description:  FPGA bitstream for GHRD
     Type:         FPGA Image
     Compression:  uncompressed
     Data Start:   0x02922a14
     Data Size:    3198976 Bytes = 3.1 MiB
     Load Address: 0x0a000000
     Hash algo:    crc32
     Hash value:   28900586
   Verifying Hash Integrity … crc32+ OK
   Loading fpga from 0x02922a14 to 0x0a000000
….FPGA reconfiguration OK!
Enable FPGA bridges
   Programming full bitstream... OK
   Uncompressing Kernel Image
   Loading Device Tree to 000000007ead6000, end 000000007eae0dec … OK
Working FDT set to 7ead6000

Starting kernel …

Deasserting all peripheral resets
[    0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034]
[    0.000000] Linux version 6.1.68-altera (oe-user@oe-host) (aarch64-poky-linux-gcc (GCC) 13.2.0, GNU ld (GNU Binutils) 2.41.0.20231213) #1 SMP PREEMPT Thu Mar 28 07:56:27 UTC 2024
[    0.000000] Machine model: SoCFPGA Agilex7-M SoCDK

…

[   13.060976] socfpga-dwmac ff800000.ethernet eth0: Link is Up - 1Gbps/Full - flow control rx/tx
[   13.069837] IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready
[   13.103121] 8021q: 802.1Q VLAN Support v1.8

Poky (Yocto Project Reference Distro) 4.3.4 agilex7dkdevagm039fes ttyS0

agilex7dkdevagm039fes login: root

root@agilex7dkdevagm039fes:~#

Run Hello World Application

Change to IntelFPGA folder, and run the hello application, which will display a meesage as shown below:

root@agilex7dkdevagm039fes:~# cd intelFPGA/
root@agilex7dkdevagm039fes:~/intelFPGA# ./hello 
Hello SoC FPGA!

Run SysCheck Application

Run the SysCheck application:

root@agilex7dkdevagm039fes:~/intelFPGA# ./syschk

It will display some system information:

                                            ALTERA SYSTEM CHECK

lo                    : 127.0.0.1           usb1                  : DWC OTG Controller
eth0                  : 192.168.1.52
                                            serial@ffc02100       : disabled
hps_led2              : OFF                 serial@ffc02000       : okay
hps_led0              : OFF
hps_led1              : OFF

Press Q to exit the appplication.

Connect to Web Server

1. Boot Linux as described in Booting Linux.

2. Determine the IP address of the board using 'ifconfig' as shown above. Note there will be network interfaces of them, either can be used.

3. Open a web browser on the host PC and type http:// on the address box, then type the IP of your board and hit Enter.

Caution: The web server is intended to allow users to control FPGA connected LEDs on the board. Due to an issue in this release, this functionality is not yet enabled. It will be enabled in the next release.

Connect over SSH

1. The lower bottom of the web page presents instructions on how to connect to the board using an SSH connection.

2. If the SSH client is not installed on your host computer, you can install it by running the following command on CentOS:

$ sudo yum install openssh-clients 

or the following command on Ubuntu:

$ sudo apt-get install openssh-client 

3. Connect to the board, and run some commands, such as pwd, ls and uname to see Linux in action:

ssh root@192.168.1.106

Building the GSRD

Setting up Environment

Create a top folder for this example, as the rest of the commands assume this location:

sudo rm -rf agilexm_gsrd
mkdir agilexm_gsrd
cd agilexm_gsrd
export TOP_FOLDER=`pwd`

Download the compiler toolchain, add it to the PATH variable, to be used by the GHRD makefile to build the HPS Debug FSBL:

cd $TOP_FOLDER
wget https://developer.arm.com/-/media/Files/downloads/gnu/11.2-2022.02/binrel\
/gcc-arm-11.2-2022.02-x86_64-aarch64-none-linux-gnu.tar.xz
tar xf gcc-arm-11.2-2022.02-x86_64-aarch64-none-linux-gnu.tar.xz
rm -f gcc-arm-11.2-2022.02-x86_64-aarch64-none-linux-gnu.tar.xz
export PATH=`pwd`/gcc-arm-11.2-2022.02-x86_64-aarch64-none-linux-gnu/bin:$PATH
export ARCH=arm64
export CROSS_COMPILE=aarch64-none-linux-gnu-

Enable Quartus tools to be called from command line:

export QUARTUS_ROOTDIR=~/intelFPGA_pro/24.1/quartus/
export PATH=$QUARTUS_ROOTDIR/bin:$QUARTUS_ROOTDIR/linux64:$QUARTUS_ROOTDIR/../qsys/bin:$PATH

Building the Hardware Design

Use the following commands to build the hardware design:

cd $TOP_FOLDER
rm -rf ghrd-socfpga agilex_soc_devkit_ghrd
git clone -b QPDS24.1_REL_GSRD_PR https://github.com/altera-opensource/ghrd-socfpga
mv ghrd-socfpga/agilex_soc_devkit_ghrd .
rm -rf ghrd-socfpga
cd agilex_soc_devkit_ghrd
export BOARD_TYPE=devkit_fp82
# perform some last minute edits on the hardware design, which did not get to github in time
sed -i 's,^\(BOARD_TYPE[ \t]*[:?]=\).*,\1 devkit_fp82,g' Makefile
sed -i 's,^\(ENABLE_HPS_EMIF_ECC[ \t]*[:?]=\).*,\1 0,g' Makefile
sed -i 's,^\(ENABLE_WATCHDOG_RST[ \t]*[:?]=\).*,\1 0,g' Makefile
sed -i 's,^\(QUARTUS_DEVICE[ \t]*[:?]=\).*,\1 AGMF039R47A1E2VR0,g' Makefile
sed -i 's,^\(BOARD_PWRMGT[ \t]*[:?]=\).*,\1 linear,g' Makefile
sed -i 's,^\(set[ \t]DEVICE[ \t]\).*,\1AGMF039R47A1E2VR0,g' design_config.tcl
sed -i 's,^\(set[ \t]BOARD[ \t]\).*,\1"devkit_fp82",g' design_config.tcl
sed -i 's,^\(set[ \t]FPGA_SGPIO_EN[ \t]\).*,\10,g' design_config.tcl
sed -i 's,^\(set[ \t]NIOSV_SUBSYS_EN[ \t]\).*,\10,g' design_config.tcl
sed -i 's,^\(set[ \t]HPS_EMIF_TYPE[ \t]\).*,\1ddr5,g' design_config.tcl
sed -i 's,^\(set[ \t]HPS_EMIF_MEM_CLK_FREQ_MHZ[ \t]\).*,\11600.0,g' design_config.tcl
sed -i 's,^\(set[ \t]HPS_EMIF_WIDTH[ \t]\).*,\132,g' design_config.tcl
sed -i 's,^\(set[ \t]F2H_WIDTH[ \t]\).*,\1256,g' design_config.tcl
sed -i 's,^\(set[ \t]HPS_F2S_IRQ_EN[ \t]\).*,\10,g' design_config.tcl
sed -i 's,^\(set[ \t]HPS_STM_EN[ \t]\).*,\10,g' design_config.tcl
sed -i 's,^\(set[ \t]CONFIG_SCHEME[ \t]\).*,\1"AVST X8",g' design_config.tcl
make scrub_clean_all
make generate_from_tcl
make all
cd ..

The following files are created:

• $TOP_FOLDER/agilex_soc_devkit_ghrd/output_files/ghrd_agmf039r47a1e2vr0.sof - FPGA configuration file, without HPS FSBL
• $TOP_FOLDER/agilex_soc_devkit_ghrd/software/hps_debug/hps_debug.ihex - HPS Debug FSBL
• $TOP_FOLDER/agilex_soc_devkit_ghrd/output_files/ghrd_agmf039r47a1e2vr0_hps_debug.sof - FPGA configuration file, with HPS Debug FSBL

Building Core RBF

cd $TOP_FOLDER
rm -f *jic* *rbf*
quartus_pfg -c agilex_soc_devkit_ghrd/output_files/ghrd_agmf039r47a1e2vr0_hps_debug.sof \
  ghrd_agmf039r47a1e2vr0.rbf \
  -o hps=1
rm ghrd_agmf039r47a1e2vr0.hps.rbf

The following files will be created:

• $TOP_FOLDER/ghrd_agmf039r47a1e2vr0.core.rbf - HPS First configuration bitstream, phase 2: FPGA fabric

Note we are also creating an HPS RBF file, but we are discarding it, as it has the HPS Debug FSBL, while the final image needs to have the U-Boot SPL created by the Yocto recipes.

Setting Up Yocto Build System

1. First, make sure you have Yocto system requirements met: https://docs.yoctoproject.org/3.4.1/ref-manual/system-requirements.html#supported-linux-distributions.

The command to install the required packages on Ubuntu 20.04 is:

sudo apt-get update
sudo apt-get upgrade
sudo apt-get install openssh-server mc libgmp3-dev libmpc-dev gawk wget git diffstat unzip texinfo gcc build-essential chrpath socat cpio python3 python3-pip python3-pexpect xz-utils debianutils iputils-ping python3-git python3-jinja2 libegl1-mesa libsdl1.2-dev pylint3 xterm python3-subunit mesa-common-dev zstd liblz4-tool git fakeroot build-essential ncurses-dev xz-utils libssl-dev bc flex libelf-dev bison  xinetd tftpd tftp nfs-kernel-server libncurses5 libc6-i386 libstdc++6:i386 libgcc++1:i386 lib32z1 device-tree-compiler curl mtd-utils u-boot-tools net-tools swig -y

On Ubuntu 20.04 you will also need to point the /bin/sh to /bin/bash, as the default is a link to /bin/dash:

 sudo ln -sf /bin/bash /bin/sh

Note: You can also use a Docker container to build the Yocto recipes, refer to https://rocketboards.org/foswiki/Documentation/DockerYoctoBuild for details. When using a Docker container, it does not matter what Linux distribution or packages you have installed on your host, as all dependencies are provided by the Docker container.

2. Clone the Yocto script and prepare the build:

cd $TOP_FOLDER
rm -rf gsrd_socfpga
git clone -b nanbield https://github.com/altera-opensource/gsrd_socfpga
cd gsrd_socfpga
. agilex7_dk_dev_agm039fes-gsrd-build.sh
build_setup

Customize Yocto Build

1. Copy the rebuilt files to $WORKSPACE/meta-intel-fpga-refdes/recipes-bsp/ghrd/files the name agilex7_dk_dev_agm039fes_gsrd_ghrd.core.rbf as expected by the recipes using the following command:

RECIPE=$WORKSPACE/meta-intel-fpga-refdes/recipes-bsp/ghrd/hw-ref-design.bb
CORE_RBF=$WORKSPACE/meta-intel-fpga-refdes/recipes-bsp/ghrd/files/agilex7_dk_dev_agm039fes_gsrd_ghrd.core.rbf
ln -s $TOP_FOLDER/ghrd_agmf039r47a1e2vr0.core.rbf $CORE_RBF

2. In the Yocto recipe $WORKSPACE/meta-intel-fpga-refdes/recipes-bsp/ghrd/hw-ref-design.bb modify the agilex_gsrd_code file location to point to the local file:

OLD_URI="\${GHRD_REPO}\/agilex7_dk_dev_agm039fes_gsrd_\${ARM64_GHRD_CORE_RBF};name=agilex7_dk_dev_agm039fes_gsrd_core"
NEW_URI="file:\/\/agilex7_dk_dev_agm039fes_gsrd_ghrd.core.rbf"
sed -i "s/$OLD_URI/$NEW_URI/g" $RECIPE

3. In the same Yocto recipe update the SHA256 checksum for the file:

CORE_SHA=$(sha256sum $CORE_RBF | cut -f1 -d" ")
OLD_SHA="SRC_URI\[agilex7_dk_dev_agm039fes_gsrd_core\.sha256sum\] = .*"
NEW_SHA="SRC_URI[agilex7_dk_dev_agm039fes_gsrd_core.sha256sum] = \"$CORE_SHA\""
sed -i "s/$OLD_SHA/$NEW_SHA/g" $RECIPE

4. Optionally change the following files in $WORKSPACE/meta-intel-fpga-refdes/recipes-bsp/u-boot/files/:

• uboot.txt - distroboot script
• uboot_script.its - its file for creating FIT image from the above script

5. Optionally change the following file in $WORKSPACE/meta-intel-fpga-refdes/recipes-kernel/linux/linux-socfpga-lts:

• fit_kernel_agilex7_dk_dev_agm039fes.its - its file for creating the kernel.itb image

Build Yocto

Build Yocto:

bitbake_image

Gather files:

package

Once the build is completed successfully, you will see the following two folders are created:

• agilex7_dk_dev_agm039fes-gsrd-rootfs: area used by OpenEmbedded build system for builds. Description of build directory structure - https://docs.yoctoproject.org/ref-manual/structure.html#the-build-directory-build
• agilex7_dk_dev_agm039fes-gsrd-images: the build script copies here relevant files built by Yocto from the agilex7_dk_dev_agf027f1es-gsrd-rootfs/tmp/deploy/images/agilex7_dk_dev_agm039fes/ folder, but also other relevant files.

The two most relevant files created in the $TOP_FOLDER/gsrd_socfpga/agilex7_dk_dev_agm039fes-gsrd-images folder are:

File	Description
sdimage.tar.gz	SD Card Image, to be written on SD card
u-boot-agilex7-socdk-gsrd-atf/u-boot-spl-dtb.hex	U-Boot SPL Hex file, to be used for generating the bootable SOF file

Building the Bootable HPS RBF File

cd $TOP_FOLDER
rm -f *rbf*
quartus_pfg -c agilex_soc_devkit_ghrd/output_files/ghrd_agmf039r47a1e2vr0.sof \
  ghrd_agmf039r47a1e2vr0.rbf \
  -o hps_path=gsrd_socfpga/agilex7_dk_dev_agm039fes-gsrd-images/u-boot-agilex7-socdk-gsrd-atf/u-boot-spl-dtb.hex \
  -o hps=1

The following files will be created:

• $TOP_FOLDER/ghrd_agmf039r47a1e2vr0.hps.rbf - RBF file to configure the device for HPS first, phase 1

Configuring through AVSTx8

This section presents the details on how the GSRD can be configured automatically at power up through AVSTx8, instead of using JTAG.

The required steps are:

1. Create the PFG file (optional, PFG file already provided here: ghrd_agmf039r47a1e2vr0.pfg)
2. Create the POF file, using the above PFG file
3. Create the CDF file, used by Quartus Programmer to know how to write the POF file
4. Write the the POF file to MAX10 board controller flash, using the Quartus Programmer
5. Configure board through AVSTx8

Warning: When using the AVSTx8 configuration method on the DevKit, the 'reboot' command from U-Boot and Linux will not work. This is because the 'reboot' command issues a Cold Reset to HPS, resulting in SDM wiping HPS and waiting for the configuration bitstream to be re-sent through AVSTx8 which is not implemented on this board. In order to make this work you need to inform the external configuration agent to re-send the configuration bitstream once the Cold Reset happens.

Creating the PFG Programmer Generator Configuration for AVSTx8

The PFG file contains information needed by the Quartus Programming File Generator to create the POF file to be stored on the QSPI flash attached to the MAX 10 board controller. The MAX 10 board controller reads the information from that QSPI file and configures the FPGA device over AVST.

This section provides the details on how the PFG file is created. A copy of the file is also attached to this page: ghrd_agmf039r47a1e2vr0.pfg.

The steps required to create the file are:

1. Start Programmer File Generator GUI:

qpfgw &

2. In the Output Files tab:

• Select Device family: Agilex 7
• Select Configuration mode: AVSTx8
• Edit Name: ghrd_agmf039r47a1e2vr0
• Check Programmer Object File (.pof)
• Check Memory Map File (.map)

The window will look similar to this:

3. Click on the Input Files tab, then click on Add Bitstream... , then select Files of type to be "Raw Binary File (*.rbf)" then browse to the ghrd_agmf039r47a1e2vr0.core.rbf file and click Open.

The window will look similar to this:

4. Go to Configuration Device tab, click Add Device, select the CFI_2Gb option and click OK.

5. Click on the OPTIONS partition to select it, then click the Edit button:

6. In the Edit Partition window, select the following:

• Address Mode: Start
• Start Address: 0x00002000

Press OK.

7. Click on CFI_2Gb then click Add Partition and select the following:

• Name: P1
• Input file: Bitstream_1
• Address mode: Start
• Start address: 0x00004000

Press OK.

8. Go to File > Save menu and save the configuration file as "ghrd_agmf039r47a1e2vr0.pfg"

Note: The created PFG file contains absolute paths. The attached PFG file was manually edited to use relative paths instead, so it can be used even when moving files in other folders on the host PC.

9. At this point you can generate the POF directly by clicking the Generate button.

Caution: Please use the addresses 0x00002000 for OPTIONS and 0x00004000 for P1, as they are required by the MAX10 board controller.

Creating the POF AVSTx8 Configuration File

The POF file is created by using the PFG file and running the following command:

cd $TOP_FOLDER
quartus_pfg -c ghrd_agmf039r47a1e2vr0.pfg

The following file is created:

• $TOP_FOLDER/ghrd_agmf039r47a1e2vr0.pof - contains the MAX 10 flash image required to configure the Agilex 7 device over AVST

Creating the CDF Programmer Configuration File

The provided ghrd_agmf039r47a1e2vr0.cdf) file contains the configuration required for the Quartus Programmer to be able to write the POF file to the QSPI attached to the MAX 10 Board Controller.

This section provides instructions on how this CDF file was created, for reference purposes.

1. Set dipswitch S24 to OFF-OFF-OFF-ON so that board configures through JTAG.

2. Power up the board

3. Start Programmer GUI:

cd $TOP_FOLDER
quartus_pgmw &

4. In the Programmer window, click on Hardware Setup and select the following:

• Currently selected hardware: Intel Agilex M-Series Development Kit - HBM2e Edition
• Hardware Frequency: 16000000

Then click Close.

5. In the Programmer window click Autodetect, then select either option from the Select Device window as shown below:

6. In the Programmer window, select the VTAP10 device, then right-click it, and select Edit > Change Device

Select the MAX 10 > 10M50DAF256 device then click OK.

7. Right click the MAX10 device, and select Edit > Attach Flash Device

Select Quad SPI Flash Memory > QSPI_2Gb option and click OK

8. Right click the QSPI_2Gb entry on the top panel, then click Change File

Browse to "ghrd_agmf039r47a1e2vr0.pof" and click Open.

9. In the Programmer window, select the Program/Configure and Verify checkboxes for both "P1" and "OPTION_BITS" partitions

10. Go to File > Save and save the configuration file as "board.cdf"

Note: The output file "ghrd_agmf039r47a1e2vr0.cdf" has an absolute path to the "ghrd_agmf039r47a1e2vr0.pof" file. The provided file was hand edited to use a relative path instead, so files could be located anywhere on the host PC file system.

11. At this stage you can also click the Start button, for the Programmer to write the file to flash. A progress bar will be shown:

12. On successfull completion, the Programmer will show 100% completed:

Writing the POF File by Using the CDF File

1. Connect the following cables to the board:

• Power: from board to power supply
• JTAG: from micro USB cable on edge of the board to host PC

2. Configure board to the default settings, except set S24 dipswitch to OFF-OFF-OFF-ON, to select MSEL=JTAG, so that board does not configure on power up.

3. Power up the board

4. Make sure you have the following files in the current folder:

• ghrd_agmf039r47a1e2vr0.cdf
• ghrd_agmf039r47a1e2vr0.pof

5. Run the following command to flash the POF file:

cd $TOP_FOLDER
wget https://www.rocketboards.org/foswiki/pub/Documentation/AgilexSoCGSRDDEVAGM039F/ghrd_agmf039r47a1e2vr0.pfg
quartus_pgm ghrd_agmf039r47a1e2vr0.cdf

Booting Linux

1. Power down the board

2. Set S24 to ON-OFF-OFF-ON to set MSEL=AVSTx8, so that the FPGA device gets configured with the POF on the next power cycle.

3. Power up the board

4. FPGA device will get configured, the U-Boot SPL will be ran, then U-Boot and then Linux. Log in with 'root' when prompted, no passowrd will be required, just like when configuring board with the RBF file.