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Building Bootloader for Cyclone V and Arria 10
Information abut latest bootloaders for Cortex-A9 based SoC FPGA devices

25 April 2024 - 06:43 | | Version 50 | Waimun Ching | arria 10, bootloader, cyclone v, socfpga, spl, u-boot

For Stratix 10 and Agilex devices, refer to Building Bootloader for Stratix 10 and Agilex.

Introduction

This page contains instructions on how to build U-Boot in the following configurations:

Device	Quartus Version	U-Boot Branch	Linux Branch
Cyclone V SoC	22.1 Std	2022.04	5.15.50-lts
Arria 10 SoC	24.1 Pro	2023.10	6.1.68-lts

Note: SoC EDS is no longer required to generate the handoff folder for Cyclone V for releases 22.1std and after. Please refer to section below if you are using version 21.1std and older.

Starting with SoC EDS Pro version 19.3 and SoC EDS Standard version 19.1, the following changes were made:

The bootloader source code was removed from SoC EDS. Instead, the user needs to clone the git trees from https://github.com/altera-opensource/u-boot-socfpga.
The same U-Boot branch is used for all SoC FPGA devices: Cyclone V SoC, Arria V SoC, Arria 10 SoC, Stratix 10 SoC, Agilex.
The bootloader generator (bsp-editor) still needs to be used for Cyclone V SoC, Arria V SoC and Arria 10 SoC, but:
- Does not support custom user settings anymore. Instead all custom user settings must be done directly in U-Boot (device tree, configuration and source code).
- Does not create a makefile which builds the bootloader. Instead the user is notified about this page, which contains instructions on how to build the bootloader.

Note that Arria V SoC flow is identical with the Cyclone V SoC one, so it is not presented separately.

Starting with Quartus Pro 20.3, the SoC EDS was discontinued, and the functionality of the tools which were previously part of SoC EDS are provided separately. For Arria 10, the bsp-editor functionality was incorporated in an U-Boot script, and the tool is not needed anymore.

U-Boot Branches

The official Intel SOCFPGA U-Boot repository is located at https://github.com/altera-opensource/u-boot-socfpga.

Notes:

A "RC" labeled branch is for internal active development use and customer early access without official customer support.
Latest stable branch (no RC labeled) is strongly recommended for development and production use outside of Intel.
See doc/README.socfpga for Quartus and Device support.

U-Boot Build Flows

Cyclone V SoC and Arria V SoC

For Cyclone V SoC and Arria V SoC, the handoff information created by Quartus compilation comes in several formats: C source code, XML and binary files. Bsp-editor takes this information and turns it into source code which is used to build U-Boot. For older versions of SoC EDS, the user could set various U-Boot parameters in bsp-editor. For the current version of SoC EDS, they have no effect.

Old Flow

The U-Boot could be built in previous versions of SoC EDS using the following flow:

Key aspects to note:

Most user options (like boot source, enabling ECC scrubbing, watchdog etc) were set through the bsp-editor GUI or the command line equivalents.
U-Boot source code was part of SoC EDS
The makefile created by the bsp-editor allowed building the bootloader with a single 'make' command

New Flow

Starting with this release of SoC EDS, the build flow is different, as depicted below:

Key differences are:

All the user options defined in the bsp-editor are not applicable anymore. They can still be set in the interface, but they have no effect
All custom user settings must be done directly in U-Boot (device tree, configuration and source code).
The makefile generated by bsp-editor does not build U-Boot, instead it instructs the user to go to this page
The U-boot source code needs to be retrieved by the user from github
A tool called qts_filter (part of U-Boot) needs to be called to convert the handoff files and bsp-editor generated files to the format required by the new U-Boot version.

Arria 10 SoC

For Arria 10 SoC, the handoff information created by Quartus compilation contains just an XML file, describing mainly the HPS pin muxing and also the clock tree settings. Bsp-editor takes this information, and creates a device tree file which is then used by U-Boot. For older versions of SoC EDS, the user could set various U-Boot parameters, like FPGA configuration filenames and firewall settings in bsp-editor. For this release the user must leave the defaults in, and manually change the device tree if needed.

Old Flow (pre 19.3)

The U-Boot could be built in previous versions of SoC EDS using the following flow:

Interim FlowFlow (19.3 through 20.1)

In 19.3 the build flow was changed, as depicted below:

New Flow (20.3 and after)

Starting with 20.3 Pro, the SoC EDS was discontinued, and the functionality of the components of SoC EDS is provided separately. The new flow does not need the bsp-editor tool anymore, as shown below:

U-Boot Examples

Prerequisites

The following are required:

Host machine running Linux. Ubuntu 20.04 was used, but other versions may work too. For Ubuntu version 20.04, you are required to installed it manually as it is not included in the OS package.
Internet connection to download the tools and clone the U-Boot git tree from github. If you are behind a firewall you will need your system administrator to enable you to get to the git trees.
Intel SoC FPGA Development Kit with your desired device: Cyclone V SoC, Arria 10 SoC, Stratix 10 SoC or Agilex
For Cyclone V SoC devices
- Quartus 22.1 Standard
For Arria 10 SoC devices
- Quartus Prime Pro version 23.4

Download and setup the toolchain required for Cyclone V SoC and Arria 10 SoC:

wget https://developer.arm.com/-/media/Files/downloads/gnu/11.2-2022.02/binrel/gcc-arm-11.2-2022.02-x86_64-arm-none-linux-gnueabihf.tar.xz
tar xf gcc-arm-11.2-2022.02-x86_64-arm-none-linux-gnueabihf.tar.xz
rm gcc-arm-11.2-2022.02-x86_64-arm-none-linux-gnueabihf.tar.xz
export PATH=`pwd`/gcc-arm-11.2-2022.02-x86_64-arm-none-linux-gnueabihf/bin:$PATH

Note that the examples presented on this page boot to Linux and they require Linux kernel, device tree and rootfilesystem to boot. However, you can omit the Linux binaries and just boot to U-Boot prompt if you want to.

For booting to Linux you can use your own Linux binaries, but a simple way to build them is included in Appendix - Building Linux Binaries. In either case the instructions assume the binaries are located in the $LINUX_BIN folder.

Cyclone V SoC - Boot from SD Card

See Appendix - Building Linux Binaries for instructions on how to build the required Linux binaries for this example.

A. Setup

Create top folder:

mkdir cv_example.sdmmc
cd cv_example.sdmmc
export TOP_FOLDER=`pwd`

Get the hardware design from github and compile it:

cd $TOP_FOLDER
rm -rf  ghrd-socfpga-QPDS22.1STD_REL_GSRD_PR QPDS22.1STD_REL_GSRD_PR.zip cv_soc_devkit_ghrd
wget https://github.com/altera-opensource/ghrd-socfpga/archive/refs/tags/QPDS22.1STD_REL_GSRD_PR.zip
unzip QPDS22.1STD_REL_GSRD_PR.zip
mv ghrd-socfpga-QPDS22.1STD_REL_GSRD_PR/cv_soc_devkit_ghrd .
rm -rf  ghrd-socfpga-QPDS22.1STD_REL_GSRD_PR QPDS22.1STD_REL_GSRD_PR.zip
cd cv_soc_devkit_ghrd
rm -rf software
~/intelFPGA/22.1std/nios2eds/nios2_command_shell.sh \
make generate_from_tcl
~/intelFPGA/22.1std/nios2eds/nios2_command_shell.sh \
make sof

B. Build U-Boot

Retrieve the U-Boot source code by cloning the git tree, and checking out the supported branch:

cd $TOP_FOLDER/cv_soc_devkit
mkdir software/bootloader && cd software/bootloader
git clone https://github.com/altera-opensource/u-boot-socfpga
cd u-boot-socfpga
# comment out next line to use the latest U-Boot branch
# git checkout -b test-bootloader -t origin/socfpga_v2022.04

Run the cv_bsp_generator.py script to take the sources from the handoff folder, format them appropriately and copy them to the U-Boot source code:

Note: Users are required to use python2 to execute cv_bsp_generator.py script. This script will be updated to python3 format in future release.

cd $TOP_FOLDER/cv_soc_devkit_ghrd/software/bootloader/u-boot-socfpga/arch/arm/mach-socfpga/cv_bsp_generator
python cv_bsp_generator.py -i $TOP_FOLDER/cv_soc_devkit_ghrd/hps_isw_handoff/soc_system_hps_0 \
-o ../../../../board/altera/cyclone5-socdk/qts

After running the cv_bsp_generator.py script, these files should be available in ../board/altera/cyclone5-socdk/qts path:

iocsr_config.h
pll_config.h
pinmux_config.h
sdram_config.h

Refer to U-Boot documentation for more details: https://github.com/altera-opensource/u-boot-socfpga/blob/socfpga_v2022.07/doc/README.socfpga

Configure and build U-Boot:

cd $TOP_FOLDER/cv_soc_devkit_ghrd/software/bootloader/u-boot-socfpga
export CROSS_COMPILE=arm-none-linux-gnueabihf-
make socfpga_cyclone5_defconfig
make -j 48

The following files will be built in the $TOP_FOLDER/cv_soc_devkit_ghrd/software/bootloader/u-boot-socfpga folder:

File	Description
spl/u-boot-spl	SPL ELF executable
u-boot	U-Boot ELF executable
u-boot-with-spl.sfp	Bootable file: four copies of SPL and one copy on U-Boot image

C. Prepare SD Card Image

This section presents how to prepare a bootable SD card, with Linux. If you do not need Linux, you can ommit the Linux parts, and you will only be able to boot to the U-Boot command prompt.

The following Linux binaries are assumed to be pre-built in the $LINUX_BIN/a9 folder:

File	Description
zImage	Compressed kernel image
socfpga_cyclone5_socdk.dtb	Linux device tree blob
core-image-minimal-cyclone5.tar.gz	Linux rootfilesystem

Create sd card top folder, and get the sd card script:

cd $TOP_FOLDER/
sudo rm -rf sd_card && mkdir sd_card && cd sd_card
wget https://releases.rocketboards.org/2021.04/gsrd/tools/make_sdimage_p3.py
chmod +x make_sdimage_p3.py

Prepare FAT partition:

cd $TOP_FOLDER/sd_card
mkdir sdfs &&  cd sdfs
cp $LINUX_BIN/a9/zImage .
cp $LINUX_BIN/a9/socfpga_cyclone5_socdk.dtb .
mkdir extlinux
echo "LABEL Linux Default" > extlinux/extlinux.conf
echo "    KERNEL ../zImage" >> extlinux/extlinux.conf
echo "    FDT ../socfpga_cyclone5_socdk.dtb" >> extlinux/extlinux.conf
echo "    APPEND root=/dev/mmcblk0p2 rw rootwait earlyprintk console=ttyS0,115200n8" >> extlinux/extlinux.conf

Prepare Rootfs partition:

cd $TOP_FOLDER/sd_card
sudo rm -rf rootfs
mkdir rootfs && cd rootfs
sudo tar xf $LINUX_BIN/a9/core-image-minimal-cyclone5.tar.gz
sudo rm -rf lib/modules/*
sudo cp -r $LINUX_BIN/a9/modules/* lib/modules

Copy over the U-boot bootable binary file:

cd $TOP_FOLDER/sd_card
cp ../cv_soc_devkit_ghrd/software/bootloader/u-boot-socfpga/u-boot-with-spl.sfp .

Prepare SD card image:

cd $TOP_FOLDER/sd_card
sudo python3 ./make_sdimage_p3.py -f \
-P u-boot-with-spl.sfp,num=3,format=raw,size=10M,type=A2  \
-P sdfs/*,num=1,format=fat32,size=100M \
-P rootfs/*,num=2,format=ext3,size=300M \
-s 512M \
-n sdcard_cv.img

D. Boot from SD Card

Write SD card image to SD card.

Set BSEL jumpers to boot from 3.3V SD device:

BSEL2=1 (left)
BSEL1=0 (right)
BSEL0=1 (left)

Power cycle the board - it will boot to Linux; Use username 'root' with no password to log in:

U-Boot SPL 2022.04-21237-gfda0d9176f-dirty (Dec 05 2022 - 22:57:54 -0600)
DDRCAL: Scrubbing ECC RAM (1024 MiB).
DDRCAL: SDRAM-ECC initialized success with 580 ms
Trying to boot from MMC1

U-Boot 2022.04-21237-gfda0d9176f-dirty (Dec 05 2022 - 22:57:54 -0600)

CPU:   Altera SoCFPGA Platform
FPGA:  Altera Cyclone V, SE/A6 or SX/C6 or ST/D6, version 0x0
BOOT:  SD/MMC Internal Transceiver (3.0V)
       Watchdog enabled
DRAM:  1 GiB
Core:  25 devices, 15 uclasses, devicetree: separate
MMC:   dwmmc0@ff704000: 0
Loading Environment from MMC... *** Warning - bad CRC, using default environment

In:    serial
Out:   serial
Err:   serial
Model: Altera SOCFPGA Cyclone V SoC Development Kit
Net:
Warning: ethernet@ff702000 (eth0) using random MAC address - 5e:9b:71:a1:db:35
eth0: ethernet@ff702000
Hit any key to stop autoboot:  0
Failed to load 'u-boot.scr'
switch to partitions #0, OK
mmc0 is current device
Scanning mmc 0:1...
Found /extlinux/extlinux.conf
Retrieving file: /extlinux/extlinux.conf
1:      Linux Default
Retrieving file: /extlinux/../zImage
append: root=/dev/mmcblk0p2 rw rootwait earlyprintk console=ttyS0,115200n8
Retrieving file: /extlinux/../socfpga_cyclone5_socdk.dtb
Kernel image @ 0x1000000 [ 0x000000 - 0x52fab0 ]
## Flattened Device Tree blob at 02000000
   Booting using the fdt blob at 0x2000000
   Loading Device Tree to 09ff6000, end 09fffa09 … OK

Starting kernel …

Deasserting all peripheral resets
[    0.000000] Booting Linux on physical CPU 0x0
[    0.000000] Linux version 5.10.70-75443-gdcd92725a9dd (theeban@test1-linux-lab) (arm-none-linux-gnueabihf-gcc (GNU Toolchain for the A-profile Architecture 10.2-2020.11 (arm-10.16)) 10.2.1 20201103, GNU ld (GNU Toolchain for the A-profile Architecture 10.2-2020.11 (arm-10.16)) 2.35.1.20201028) #1 SMP Mon Dec 27 21:58:00 CST 2021
[    0.000000] CPU: ARMv7 Processor [413fc090] revision 0 (ARMv7), cr=10c5387d
[    0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
[    0.000000] OF: fdt: Machine model: Altera SOCFPGA Cyclone V SoC Development Kit

…

[    6.211413] socfpga-dwmac ff702000.ethernet eth0: No Safety Features support found
[    6.219217] socfpga-dwmac ff702000.ethernet eth0: registered PTP clock
[    6.226573] socfpga-dwmac ff702000.ethernet eth0: configuring for phy/rgmii link mode
udhcpc: started, v1.34.1
udhcpc: broadcasting discover
udhcpc: broadcasting discover
udhcpc: broadcasting discover
udhcpc: no lease, forking to background
done.
Starting syslogd/klogd: done

Poky (Yocto Project Reference Distro) 3.4.1 cyclone5 /dev/ttyS0

cyclone5 login: root
root@cyclone5:~#

Cyclone V SoC - Boot from QSPI

Booting from QSPI is very similar with booting from SD card, with the following differences:

Additional U-Boot configuration is performed, to store envioronment in QSPI instead of SD card
Binaries are written to QSPI instead of SD card

See Appendix - Building Linux Binaries for instructions on how to build the required Linux binaries for this example.

A. Setup

Create top folder:

mkdir cv_example.qspi
cd cv_example.qspi
export TOP_FOLDER=`pwd`

Get the hardware design from github and compile it:

cd $TOP_FOLDER
rm -rf  ghrd-socfpga-QPDS22.1STD_REL_GSRD_PR QPDS22.1STD_REL_GSRD_PR.zip cv_soc_devkit_ghrd
wget https://github.com/altera-opensource/ghrd-socfpga/archive/refs/tags/QPDS22.1STD_REL_GSRD_PR.zip
unzip QPDS22.1STD_REL_GSRD_PR.zip
mv ghrd-socfpga-QPDS22.1STD_REL_GSRD_PR/cv_soc_devkit_ghrd .
rm -rf  ghrd-socfpga-QPDS22.1STD_REL_GSRD_PR QPDS22.1STD_REL_GSRD_PR.zip
cd cv_soc_devkit_ghrd
rm -rf software
~/intelFPGA/22.1std/nios2eds/nios2_command_shell.sh \
make generate_from_tcl
~/intelFPGA/22.1std/nios2eds/nios2_command_shell.sh \
make sof

B. U-Boot

Retrieve the U-Boot source code by cloning the git tree, and checking out the supported branch:

cd $TOP_FOLDER/cv_soc_devkit_ghrd/software/bootloader
git clone https://github.com/altera-opensource/u-boot-socfpga
cd u-boot-socfpga
# comment out next line to use the latest U-Boot branch
# git checkout -b test-bootloader -t origin/socfpga_v2022.04

Run the qts_filter to take the sources from the handoff folder and the ones generated by bsp-create-settings, format them appropriately and copy them to the U-Boot source code:

Note: Users are required to use python2 to execute cv_bsp_generator.py script. This script will be updated to python3 format in future release.

cd $TOP_FOLDER/cv_soc_devkit_ghrd/software/bootloader/u-boot-socfpga/arch/arm/mach-socfpga/cv_bsp_generator
python cv_bsp_generator.py -i $TOP_FOLDER/cv_soc_devkit_ghrd/hps_isw_handoff/soc_system_hps_0 \
-o ../../../../board/altera/cyclone5-socdk/qts

After running the cv_bsp_generator.py script, these files should be available in ../board/altera/cyclone5-socdk/qts path:

iocsr_config.h
pll_config.h
pinmux_config.h
sdram_config.h

Refer to U-Boot documentation for more details: https://github.com/altera-opensource/u-boot-socfpga/blob/socfpga_v2022.07/doc/README.socfpga

Configure and build U-Boot:

cd $TOP_FOLDER/cv_soc_devkit_ghrd/software/bootloader/u-boot-socfpga
export CROSS_COMPILE=arm-none-linux-gnueabihf-
make socfpga_cyclone5_qspi_defconfig
make -j 48

The following files will be built in the $TOP_FOLDER/cv_soc_devkit_ghrd/software/bootloader/u-boot-socfpga folder:

File	Description
spl/u-boot-spl	SPL ELF executable
u-boot	U-Boot ELF executable
u-boot-with-spl.sfp	Bootable file: four copies of SPL and one copy on U-Boot image

C. QSPI Binaries

This section presents how to boot in Linux, from QSPI. If you do not need Linux, you can ommit the Linux parts, and you will only be able to boot to the U-Boot command prompt.

The following Linux binaries are assumed to be pre-built in the $LINUX_BIN/a9 folder:

File	Description
zImage	Compressed kernel image
socfpga_cyclone5_socdk.dtb	Linux device tree blob
core-image-minimal-cyclone5.tar.gz	Linux rootfilesystem

Create qspi_bin folder and bring all the files:

cd $TOP_FOLDER/
sudo rm -rf qspi_bin && mkdir qspi_bin && cd qspi_bin
cp ../cv_soc_devkit_ghrd/software/bootloader/u-boot-socfpga/u-boot-with-spl.sfp .
cp $LINUX_BIN/a9/zImage .
cp $LINUX_BIN/a9/socfpga_cyclone5_socdk.dtb .

Build the rootfs JFFS2 image:

cd $TOP_FOLDER/qspi_bin
sudo rm -rf core-image-minimal-cyclone5-rootfs
mkdir core-image-minimal-cyclone5-rootfs
cd core-image-minimal-cyclone5-rootfs
sudo tar xf $LINUX_BIN/a9/core-image-minimal-cyclone5.tar.gz
sudo rm -rf lib/modules/*
cd ..
sudo mkfs.jffs2 -r core-image-minimal-cyclone5-rootfs -s 256 -e 64KiB --squash -o core-image-minimal-cyclone5-rootfs.jffs2
sudo chown $USER:$USER core-image-minimal-cyclone5-rootfs.jffs2
sudo rm -rf core-image-minimal-cyclone5-rootfs

The following files are now prepared:

File	Description
u-boot-with-spl.sfp	Four SPL images and U-Boot image
socfpga_cyclone5_socdk.dtb	Linux device tree blob
zImage	Compressed linu kernel
core-image-minimal-cyclone5-rootfs.jffs2	Linux rootfs image

D. Boot

Set BSEL jumpers to boot from 3.3V QSPI device:

BSEL2=1 (left)
BSEL1=1 (left)
BSEL0=1 (left)

Address	File	Description
0x0000000	u-boot-with-spl.sfp	Four SPL binaries and U-Boot image
0x0200000	n/a	U-Boot environment
0x0220000	socfpga_cyclone5_socdk.dtb	Linux device tree
0x0230000	zImage	Linux kernel
0x0800000	core-image-minimal-cyclone5-rootfs.jffs2	Linux rootfs

Flash the QSPI binaries:

cd $TOP_FOLDER/qspi_bin

~/intelFPGA/22.1std/nios2eds/nios2_command_shell.sh \
quartus_hps -c 1 -o pv -a 0x000000 u-boot-with-spl.sfp

~/intelFPGA/22.1std/nios2eds/nios2_command_shell.sh \
quartus_hps -c 1 -o pv -a 0x220000 socfpga_cyclone5_socdk.dtb

~/intelFPGA/22.1std/nios2eds/nios2_command_shell.sh \
quartus_hps -c 1 -o pv -a 0x230000 zImage

~/intelFPGA/22.1std/nios2eds/nios2_command_shell.sh \
quartus_hps -c 1 -o pv -a 0x800000 -s 0x3800000 core-image-minimal-cyclone5-rootfs.jffs2

Note that quartus_hps is slow, and a better alternative is to load U-Boot through DS-5 debugger, download the files through TFTP and write them with U-Boot:

Erase the QSPI with quartus_hps:

~/intelFPGA/22.1std/nios2eds/nios2_command_shell.sh \
quartus_hps -c 1 -o E

Copy the binaries to the TFTP folder on your host machine
Run U-Boot from the debugger as shown in Cyclone V SoC - Run U-Boot from Debugger
Connnect your U-Boot to the network, and specify the IP address of you host machine:

setenv autoload no
dhcp
setenv serverip <your_server_ip>

In U-Boot, download binaries over TFTP, and write the to QSPI:

sf probe
tftp ${loadaddr} u-boot-with-spl.sfp;sf write ${loadaddr} 0x000000 ${filesize}
tftp ${loadaddr} socfpga_cyclone5_socdk.dtb;sf write ${loadaddr} 0x220000 ${filesize}
tftp ${loadaddr} zImage;sf write ${loadaddr} 0x230000 ${filesize}
tftp ${loadaddr} core-image-minimal-cyclone5-rootfs.jffs2;sf write ${loadaddr} 0x800000 ${filesize}

Power cycle the board, and boot to Linux:

U-Boot SPL 2021.07-16360-gee63370553-dirty (Dec 20 2021 - 12:31:46 -0600)
DDRCAL: Scrubbing ECC RAM (1024 MiB).
DDRCAL: SDRAM-ECC initialized success with 579 ms
Trying to boot from SPI

U-Boot 2021.07-16360-gee63370553-dirty (Dec 20 2021 - 12:31:46 -0600)

CPU:   Altera SoCFPGA Platform
FPGA:  Altera Cyclone V, SE/A6 or SX/C6 or ST/D6, version 0x0
BOOT:  QSPI Flash (3.0V)
       Watchdog enabled
DRAM:  1 GiB
MMC:   dwmmc0@ff704000: 0
Loading Environment from SPIFlash... SF: Detected n25q512ax3 with page size 256 Bytes, erase size 64 KiB, total 64 MiB
*** Warning - bad CRC, using default environment

In:    serial
Out:   serial
Err:   serial
Model: Altera SOCFPGA Cyclone V SoC Development Kit
Net:   
Warning: ethernet@ff702000 (eth0) using random MAC address - 2e:d9:0c:64:69:0b
eth0: ethernet@ff702000
Hit any key to stop autoboot:  0 
SF: Detected n25q512ax3 with page size 256 Bytes, erase size 64 KiB, total 64 MiB
device 0 offset 0x230000, size 0x5d0000
SF: 6094848 bytes @ 0x230000 Read: OK
device 0 offset 0x220000, size 0x10000
SF: 65536 bytes @ 0x220000 Read: OK
Kernel image @ 0x1000000 [ 0x000000 - 0x52fbb0 ]
## Flattened Device Tree blob at 02000000
   Booting using the fdt blob at 0x2000000
   Loading Device Tree to 09ff6000, end 09fffa09 … OK

Starting kernel …

Deasserting all peripheral resets
[    0.000000] Booting Linux on physical CPU 0x0
[    0.000000] Linux version 5.10.70-75443-gdcd92725a9dd-dirty (radu@linux-machine) (arm-none-linux-gnueabihf-gcc (GNU Toolchain for the A-profile Architecture 10.2-2020.11 (arm-10.16)) 10.2.1 20201103, GNU ld (GNU Toolchain for the A-profile Architecture 10.2-2020.11 (arm-10.16)) 2.35.1.20201028) #1 SMP Mon Dec 20 11:18:16 CST 2021
[    0.000000] CPU: ARMv7 Processor [413fc090] revision 0 (ARMv7), cr=10c5387d
[    0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
[    0.000000] OF: fdt: Machine model: Altera SOCFPGA Cyclone V SoC Development Kit

…

[    5.231684] socfpga-dwmac ff702000.ethernet eth0: configuring for phy/rgmii link mode
[    8.341623] socfpga-dwmac ff702000.ethernet eth0: Link is Up - 1Gbps/Full - flow control off
[    8.350073] IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready

Poky (Yocto Project Reference Distro) 3.4.1 cyclone5 /dev/ttyS0

cyclone5 login: root
root@cyclone5:~#

Arria 10 SoC - Boot from SD Card

See Appendix - Building Linux Binaries for instructions on how to build the required Linux binaries for this example.

A. Setup

Create top folder:

sudo rm -rf a10_example.sdmmc
mkdir a10_example.sdmmc
cd a10_example.sdmmc
export TOP_FOLDER=`pwd`

Enable Quartus tools to be called from command line:

export QUARTUS_ROOTDIR=~/intelFPGA_pro/24.1/quartus/
export PATH=$QUARTUS_ROOTDIR/bin:$QUARTUS_ROOTDIR/linux64:$QUARTUS_ROOTDIR/../qsys/bin:$PATH

Bring a copy of the hardware design - already compiled, and remove the software folder:

cd $TOP_FOLDER
rm -rf  ghrd-socfpga-QPDS24.1_REL_GSRD_PR QPDS24.1_REL_GSRD_PR.zip a10_soc_devkit_ghrd
wget https://github.com/altera-opensource/ghrd-socfpga/archive/refs/tags/QPDS24.1_REL_GSRD_PR.zip
unzip QPDS24.1_REL_GSRD_PR.zip
mv ghrd-socfpga-QPDS24.1_REL_GSRD_PR/a10_soc_devkit_ghrd_pro a10_soc_devkit_ghrd
rm -rf  ghrd-socfpga-QPDS24.1_REL_GSRD_PR QPDS24.1_REL_GSRD_PR.zip
cd a10_soc_devkit_ghrd
make clean && make scrub_clean && rm -rf software
make generate_from_tcl
make rbf

B. Build U-Boot

Retrieve the U-Boot source code by cloning the git tree, and checking out the supported branch:

cd $TOP_FOLDER/a10_soc_devkit_ghrd/
mkdir -p software/bootloader
cd software/bootloader/
git clone https://github.com/altera-opensource/u-boot-socfpga
cd u-boot-socfpga
# comment out next line to use the latest U-Boot branch
# git checkout -b test -t origin/socfpga_v2023.04

Convert hps.xml handoff file to include file to be used by the device tree:

cd $TOP_FOLDER/a10_soc_devkit_ghrd/software/bootloader/u-boot-socfpga
./arch/arm/mach-socfpga/qts-filter-a10.sh \
../../../hps_isw_handoff/hps.xml \
arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.h

Configure and build U-Boot:

cd $TOP_FOLDER/a10_soc_devkit_ghrd/software/bootloader/u-boot-socfpga
export CROSS_COMPILE=arm-none-linux-gnueabihf-
make socfpga_arria10_defconfig
make -j 48

This will create the following files:

File	Description
spl/u-boot-splx4.sfp	Bootable image, with four SPL binaries, in the format required by BootROM
u-boot.img	U-Boot image

Create the FIT image with the FPGA programming files, used by SPL to configure FPGA:

cd $TOP_FOLDER/a10_soc_devkit_ghrd/software/bootloader/u-boot-socfpga
ln -s ../../../output_files/ghrd_10as066n2.core.rbf .
ln -s ../../../output_files/ghrd_10as066n2.periph.rbf .
tools/mkimage -E -f board/altera/arria10-socdk/fit_spl_fpga.its fit_spl_fpga.itb

This creates the file fit_spl_fpga.itb.

C. Build SD Card Image

Create SD card folder and retrieve the SD card script:

cd $TOP_FOLDER/
sudo rm -rf sd_card && mkdir sd_card && cd sd_card
wget https://releases.rocketboards.org/2021.04/gsrd/tools/make_sdimage_p3.py
chmod +x make_sdimage_p3.py

Create the folder for the FAT partition and gather the files:

cd $TOP_FOLDER/sd_card
mkdir sdfs &&  cd sdfs
cp $LINUX_BIN/a9/zImage .
cp $LINUX_BIN/a9/socfpga_arria10_socdk_sdmmc.dtb .
cp ../../a10_soc_devkit_ghrd/software/bootloader/u-boot-socfpga/fit_spl_fpga.itb .
cp ../../a10_soc_devkit_ghrd/software/bootloader/u-boot-socfpga/u-boot.img .
mkdir extlinux
echo "LABEL Arria10 SOCDK SDMMC" > extlinux/extlinux.conf
echo "    KERNEL ../zImage" >> extlinux/extlinux.conf
echo "    FDT ../socfpga_arria10_socdk_sdmmc.dtb" >> extlinux/extlinux.conf
echo "    APPEND root=/dev/mmcblk0p2 rw rootwait earlyprintk console=ttyS0,115200n8" >> extlinux/extlinux.conf

Create the folder for the rootfs partition:

cd $TOP_FOLDER/sd_card
mkdir rootfs && cd rootfs
sudo tar xf $LINUX_BIN/a9/core-image-minimal-arria10.tar.gz
sudo rm -rf lib/modules/*

Bring over the SPL binary:

cd $TOP_FOLDER/sd_card
cp ../a10_soc_devkit_ghrd/software/bootloader/u-boot-socfpga/spl/u-boot-splx4.sfp .

Create the SD card image:

cd $TOP_FOLDER/sd_card
sudo python3 ./make_sdimage_p3.py -f \
-P u-boot-splx4.sfp,num=3,format=raw,size=10M,type=A2  \
-P sdfs/*,num=1,format=fat32,size=32M \
-P rootfs/*,num=2,format=ext3,size=32M \
-s 80M \
-n sdcard_a10.img

This will create the file $TOP_FOLDER/sd_card/sdcard_a10.img.

D. Boot

Write SD card image to SD card, insert in slot and power up the board.

Board will boot through SPL and U-Boot through Linux prompt. Use 'root' as login, with no password:

U-Boot SPL 2022.01 (Jul 14 2022 - 04:47:18 +0000)
FPGA: Checking FPGA configuration setting …
FPGA: Start to program peripheral/full bitstream …
FPGA: Early Release Succeeded.
FPGA: Checking FPGA configuration setting …
FPGA: Start to program peripheral/full bitstream …
FPGA: Early Release Succeeded.

U-Boot SPL 2022.01 (Jul 14 2022 - 04:47:18 +0000)
DDRCAL: Success
DDRCAL: Scrubbing ECC RAM (1024 MiB).
DDRCAL: SDRAM-ECC initialized success with 148 ms
FPGA: Checking FPGA configuration setting …
FPGA: Skipping configuration …
WDT:   Started watchdog@ffd00300 with servicing (10s timeout)
Trying to boot from MMC1

U-Boot 2022.01 (Jul 14 2022 - 04:47:18 +0000)socfpga_arria10

CPU:   Altera SoCFPGA Arria 10
BOOT:  SD/MMC External Transceiver (1.8V)
Model: Altera SOCFPGA Arria 10
DRAM:  1 GiB
WDT:   Started watchdog@ffd00300 with servicing (10s timeout)
MMC:   dwmmc0@ff808000: 0
Loading Environment from MMC... *** Warning - bad CRC, using default environment

In:    serial
Out:   serial
Err:   serial
Model: Altera SOCFPGA Arria 10
Net:
Warning: ethernet@ff800000 (eth0) using random MAC address - 1a:4c:fe:b0:88:ae
eth0: ethernet@ff800000
Hit any key to stop autoboot:  0
Failed to load 'u-boot.scr'
15024780 bytes read in 717 ms (20 MiB/s)
Full Configuration Succeeded.
FPGA: Enter user mode.
switch to partitions #0, OK
mmc0 is current device
Scanning mmc 0:1...
Found /extlinux/extlinux.conf
Retrieving file: /extlinux/extlinux.conf
1:      Arria10 SOCDK SDMMC
Retrieving file: /extlinux/../zImage
append: root=/dev/mmcblk0p2 rootwait rw earlyprintk memmap=16M$0x3F000000 console=ttyS0,115200n8
Retrieving file: /extlinux/../socfpga_arria10_socdk_sdmmc.dtb
Kernel image @ 0x1000000 [ 0x000000 - 0x5993a0 ]
## Flattened Device Tree blob at 02000000
   Booting using the fdt blob at 0x2000000
   Loading Device Tree to 09ff5000, end 09fff26c … OK

Starting kernel …

Deasserting all peripheral resets
[    0.000000] Booting Linux on physical CPU 0x0
[    0.000000] Linux version 5.15.30-altera (oe-user@oe-host) (arm-poky-linux-gnueabi-gcc (GCC) 11.3.0, GNU ld (GNU Binutils) 2.38.20220516) #1 SMP Fri Jun 24 03:52:26 UTC 2022
[    0.000000] CPU: ARMv7 Processor [414fc091] revision 1 (ARMv7), cr=10c5387d
[    0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
[    0.000000] OF: fdt: Machine model: Altera SOCFPGA Arria 10

…

[  OK  ] Started Network Configuration.
[  OK  ] Reached target Network.
[  OK  ] Started NFS status monitor for NFSv2/3 locking..
[  OK  ] Started Hostname Service.
[    9.443394] random: crng init done
[  OK  ] Finished Load/Save Random Seed.
[   11.044930] socfpga-dwmac ff800000.ethernet eth0: Link is Up - 1Gbps/Full - flow control rx/tx
[   11.065488] IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready

Poky (Yocto Project Reference Distro) 4.0.2 arria10 ttyS0

arria10 login: root
Last login: Fri Apr 29 03:03:53 +0000 2022 on /dev/ttyS0.
root@arria10:~#

Arria 10 SoC - Boot from QSPI

See Appendix - Building Linux Binaries for instructions on how to build the required Linux binaries for this example.

A. Setup

Create top folder:

sudo rm -rf a10_example.qspi
mkdir a10_example.qspi
cd a10_example.qspi
export TOP_FOLDER=`pwd`

Enable Quartus tools to be called from command line:

export QUARTUS_ROOTDIR=~/intelFPGA_pro/24.1/quartus/
export PATH=$QUARTUS_ROOTDIR/bin:$QUARTUS_ROOTDIR/linux64:$QUARTUS_ROOTDIR/../qsys/bin:$PATH

Bring a copy of the hardware design, update it for QSPI and build it:

cd $TOP_FOLDER
rm -rf  ghrd-socfpga-QPDS24.1_REL_GSRD_PR QPDS24.1_REL_GSRD_PR.zip a10_soc_devkit_ghrd
wget https://github.com/altera-opensource/ghrd-socfpga/archive/refs/tags/QPDS24.1_REL_GSRD_PR.zip
unzip QPDS24.1_REL_GSRD_PR.zip
mv ghrd-socfpga-QPDS24.1_REL_GSRD_PR/a10_soc_devkit_ghrd_pro a10_soc_devkit_ghrd
rm -rf  ghrd-socfpga-QPDS24.1_REL_GSRD_PR QPDS24.1_REL_GSRD_PR.zip
cd a10_soc_devkit_ghrd
make clean && make scrub_clean && rm -rf software
sed -i 's/HPS_BOOT_DEVICE .= .*/HPS_BOOT_DEVICE := QSPI/g' Makefile
make generate_from_tcl
make rbf

B. Build U-Boot

Get U-Boot source code

cd $TOP_FOLDER/a10_soc_devkit_ghrd/
mkdir -p software/bootloader
cd software/bootloader
git clone https://github.com/altera-opensource/u-boot-socfpga
cd u-boot-socfpga
# comment out next line to use the latest U-Boot branch
# git checkout -b test-bootloader -t origin/socfpga_v2023.04

Convert hps.xml handoff file to include file to be used by the device tree:

cd $TOP_FOLDER/a10_soc_devkit_ghrd/software/bootloader/u-boot-socfpga
./arch/arm/mach-socfpga/qts-filter-a10.sh \
../../../hps_isw_handoff/hps.xml \
arch/arm/dts/socfpga_arria10_socdk_qspi_handoff.h

Configure and build U-Boot:

cd $TOP_FOLDER/a10_soc_devkit_ghrd/software/bootloader/u-boot-socfpga
export CROSS_COMPILE=arm-none-linux-gnueabihf-
make socfpga_arria10_qspi_defconfig
make -j 48

This will create the following files:

File	Description
spl/u-boot-splx4.sfp	Bootable image, with four SPL binaries, in the format required by BootROM
u-boot.img	U-Boot image

Create the FIT image with the FPGA programming files, used by SPL to configure FPGA:

cd $TOP_FOLDER/a10_soc_devkit_ghrd/software/bootloader/u-boot-socfpga
cp ../../../output_files/ghrd_10as066n2.core.rbf .
cp ../../../output_files/ghrd_10as066n2.periph.rbf .
tools/mkimage -E -f board/altera/arria10-socdk/fit_spl_fpga.its fit_spl_fpga.itb

This creates the file fit_spl_fpga.itb.

Create FIT image for the U-Boot:

cd $TOP_FOLDER/a10_soc_devkit_ghrd/software/bootloader/u-boot-socfpga
tools/mkimage -E -f board/altera/arria10-socdk/fit_uboot.its  fit_uboot.itb

This creates the file fit_uboot.itb.

Create FIT image for the Linux kernel and device tree:

cd $TOP_FOLDER/a10_soc_devkit_ghrd/software/bootloader/u-boot-socfpga
cp $LINUX_BIN/a9/Image .
cp $LINUX_BIN/a9/socfpga_arria10_socdk_qspi.dtb .
tools/mkimage -f  board/altera/arria10-socdk/fit_kernel_qspi.its kernel.itb

This creates the file fit_kernel.itb.

C. Build QSPI Binaries

Create qspi_bin folder and bring all the files:

cd $TOP_FOLDER/
rm -rf qspi_bin && mkdir qspi_bin && cd qspi_bin
cp ../a10_soc_devkit_ghrd/software/bootloader/u-boot-socfpga/spl/u-boot-splx4.sfp .
cp ../a10_soc_devkit_ghrd/software/bootloader/u-boot-socfpga/fit_uboot.itb .
cp ../a10_soc_devkit_ghrd/software/bootloader/u-boot-socfpga/fit_spl_fpga.itb .
cp ../a10_soc_devkit_ghrd/software/bootloader/u-boot-socfpga/kernel.itb .

Prepare JFFS2 rootfs image for booting Linux from QSPI:

cd $TOP_FOLDER/qspi_bin/
sudo rm -rf core-image-minimal-arria10-rootfs
mkdir core-image-minimal-arria10-rootfs
cd core-image-minimal-arria10-rootfs
tar xf $LINUX_BIN/a9/core-image-minimal-arria10.tar.gz
sudo rm -rf lib/modules/*
cd ..
sudo mkfs.jffs2 -r core-image-minimal-arria10-rootfs -s 256 -e 64KiB --squash -o core-image-minimal-arria10-rootfs.jffs2
sudo chown $USER:$USER core-image-minimal-arria10-rootfs.jffs2
sudo rm -rf core-image-minimal-arria10-rootfs

At this point the following binaries are available in the $TOP_FOLDER/qspi_bin:

File	Description
u-boot-splx4.sfp	Four SPL binaries, with BootROM header
fit_uboot.itb	U-Boot image
fit_spl_fpga.itb	FPGA configuration files
kernel.itb	Linux kerned and device tree
core-image-minimal-arria10-rootfs.jffs2	Linux rootfs

D. Boot

QSPI Flash Layout:

Address	File	Description
0x0000000	u-boot-splx4.sfp	Four SPL binaries, with BootROM header
0x0100000	fit_uboot.itb	U-Boot image
0x0200000	n/a	U-Boot environment
0x0300000	fit_spl_fpga.itb	FPGA configuration files
0x1200000	kernel.itb	Linux kerned and device tree
0x2720000	core-image-minimal-arria10-rootfs.jffs2	Linux rootfs

Enable Quartus tools to be called from command line:

export QUARTUS_ROOTDIR=~/intelFPGA_pro/24.1/quartus/
export PATH=$QUARTUS_ROOTDIR/bin:$QUARTUS_ROOTDIR/linux64:$QUARTUS_ROOTDIR/../qsys/bin:$PATH

Program QSPI flash with all the binaries:

cd $TOP_FOLDER/qspi_bin

quartus_hps -c 1 -o e

quartus_hps -c 1 -o pv -a 0x0000000 u-boot-splx4.sfp

quartus_hps -c 1 -o pv -a 0x0100000 fit_uboot.itb

quartus_hps -c 1 -o pv -a 0x0300000 fit_spl_fpga.itb

quartus_hps -c 1 -o pv -a 0x1200000 kernel.itb

quartus_hps -c 1 -o pv -a 0x2720000 core-image-minimal-arria10-rootfs.jffs2

Note that quartus_hps is slow, and a better alternative is to load U-Boot through DS-5 debugger, download the files through TFTP and write them with U-Boot:

Erase the QSPI flash using quartus_hps, as that is faster than U-Boot:

quartus_hps -c 1 -o E

Copy the binaries to the TFTP folder on your host machine
Run U-Boot from the debugger as shown in Arria 10 SoC - Run U-Boot from Debugger
Connnect your U-Boot to the network, and specify the IP address of you host machine:

setenv autoload no
dhcp
setenv serverip <your_server_ip>

In U-Boot, download binaries over TFTP, and write the to QSPI:

sf probe
Erase QSPI if not done with quartus_hps::sf erase 0 8000000
tftp ${loadaddr} u-boot-splx4.sfp;sf write ${loadaddr} 0x0000000  ${filesize}
tftp ${loadaddr} fit_uboot.itb; sf write ${loadaddr} 0x0100000 ${filesize} 
tftp ${loadaddr} fit_spl_fpga.itb; sf write ${loadaddr} 0x0300000 ${filesize} 
tftp ${loadaddr} kernel.itb; sf write ${loadaddr} 0x1200000 ${filesize} 
tftp ${loadaddr} core-image-minimal-arria10-rootfs.jffs2 ;sf write ${loadaddr} 0x2720000 ${filesize}

Power cycle the board - it will boot to Linux login. Use 'root' as username with no password:

U-Boot SPL 2022.04-21237-gfda0d9176f-dirty (Nov 30 2022 - 22:13:33 -0600)
FPGA: Checking FPGA configuration setting …
FPGA: Start to program peripheral/full bitstream …
FPGA: Early Release Succeeded.
FPGA: Checking FPGA configuration setting …
FPGA: Start to program peripheral/full bitstream …
FPGA: Early Release Succeeded.

U-Boot SPL 2022.04-21237-gfda0d9176f-dirty (Nov 30 2022 - 22:13:33 -0600)
DDRCAL: Success
DDRCAL: Scrubbing ECC RAM (1024 MiB).
DDRCAL: SDRAM-ECC initialized success with 148 ms
FPGA: Checking FPGA configuration setting …
FPGA: Start to program core bitstream …
Full Configuration Succeeded.
FPGA: Enter user mode.
WDT:   Started watchdog@ffd00300 with servicing (10s timeout)
Trying to boot from SPI

U-Boot 2022.04-21237-gfda0d9176f-dirty (Nov 30 2022 - 22:13:33 -0600)socfpga_arria10

CPU:   Altera SoCFPGA Arria 10
BOOT:  QSPI Flash (1.8V)
Model: Altera SOCFPGA Arria 10
DRAM:  1 GiB
Core:  69 devices, 16 uclasses, devicetree: separate
WDT:   Started watchdog@ffd00300 with servicing (10s timeout)
Loading Environment from SPIFlash... SF: Detected mt25qu01g with page size 256 Bytes, erase size 4 KiB, total 128 MiB
*** Warning - bad CRC, using default environment

In:    serial
Out:   serial
Err:   serial
Model: Altera SOCFPGA Arria 10
Net:
Warning: ethernet@ff800000 (eth0) using random MAC address - 62:b4:b4:24:69:13
eth0: ethernet@ff800000
Hit any key to stop autoboot:  0
SF: Detected mt25qu01g with page size 256 Bytes, erase size 4 KiB, total 128 MiB
device 0 offset 0x1200000, size 0x6e00000
SF: 115343360 bytes @ 0x1200000 Read: OK
## Loading kernel from FIT Image at 02100000 …
   Using 'conf' configuration
   Trying 'kernel' kernel subimage
     Description:  Linux Kernel
     Type:         Kernel Image
     Compression:  uncompressed
     Data Start:   0x021000cc
     Data Size:    14366044 Bytes = 13.7 MiB
     Architecture: ARM
     OS:           Linux
     Load Address: 0x00008000
     Entry Point:  0x00008000
   Verifying Hash Integrity … OK
## Loading fdt from FIT Image at 02100000 …
   Using 'conf' configuration
   Trying 'fdt' fdt subimage
     Description:  Linux DTB
     Type:         Flat Device Tree
     Compression:  uncompressed
     Data Start:   0x02eb36c4
     Data Size:    25567 Bytes = 25 KiB
     Architecture: ARM
   Verifying Hash Integrity … OK
   Booting using the fdt blob at 0x2eb36c4
   Loading Kernel Image
   Loading Device Tree to 09ff6000, end 09fff3de … OK

Starting kernel …

Deasserting all peripheral resets
[    0.000000] Booting Linux on physical CPU 0x0
[    0.000000] Linux version 5.10.70-75443-gdcd92725a9dd (theeban@test1-linux-lab) (arm-none-linux-gnueabihf-gcc (GNU Toolchain for the A-profile Architecture 10.2-2020.11 (arm-10.16)) 10.2.1 20201103, GNU ld (GNU Toolchain for the A-profile Architecture 10.2-2020.11 (arm-10.16)) 2.35.1.20201028) #1 SMP Mon Dec 27 21:58:00 CST 2021
[    0.000000] CPU: ARMv7 Processor [414fc091] revision 1 (ARMv7), cr=10c5387d
[    0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
[    0.000000] OF: fdt: Machine model: Altera SOCFPGA Arria 10

…

udhcpc: started, v1.34.1
udhcpc: broadcasting discover
udhcpc: broadcasting discover
[    8.233258] socfpga-dwmac ff800000.ethernet eth0: Link is Up - 1Gbps/Full - flow control rx/tx
[    8.241887] IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready
udhcpc: broadcasting discover
udhcpc: broadcasting select for 10.122.105.64, server 10.2.71.6
udhcpc: lease of 10.122.105.64 obtained from 10.2.71.6, lease time 3600
/etc/udhcpc.d/50default: Adding DNS 10.248.2.1
/etc/udhcpc.d/50default: Adding DNS 10.2.71.6
/etc/udhcpc.d/50default: Adding DNS 10.31.40.4
done.
hwclock: can't open '/dev/misc/rtc': No such file or directory
Starting syslogd/klogd: done

Poky (Yocto Project Reference Distro) 3.4.1 arria10 /dev/ttyS0

arria10 login:

Arria 10 SoC - Boot from NAND

The instructions in this section assume the standard 1Gb NAND part is used (part number: MT29F1G08ABBEAH4:E, marking: NW360). Newer dev kits may be using a 8Gb part (part number: MT29F8G08ABBCAH4-IT:C, marking: NQ299).

The following changes will be needed if the newer 8Gb part number is used:

Make sure that all items in flash are aligned to the new erase block size (256KB)
Make sure the JFFS2 image uses the new parameters (256KB block erase size, 2048 page size)
Increase the size of the rootfs partition, to use the rest of the flash

See Appendix - Building Linux Binaries for instructions on how to build the required Linux binaries for this example.

A. Setup

Create top folder:

sudo rm -rf a10_example.nand
mkdir a10_example.nand
cd a10_example.nand
export TOP_FOLDER=`pwd`

Enable Quartus tools to be called from command line:

export QUARTUS_ROOTDIR=~/intelFPGA_pro/24.1/quartus/
export PATH=$QUARTUS_ROOTDIR/bin:$QUARTUS_ROOTDIR/linux64:$QUARTUS_ROOTDIR/../qsys/bin:$PATH

Bring a copy of the hardware design, update it for QSPI and build it:

cd $TOP_FOLDER
rm -rf  ghrd-socfpga-QPDS24.1_REL_GSRD_PR QPDS24.1_REL_GSRD_PR.zip a10_soc_devkit_ghrd
wget https://github.com/altera-opensource/ghrd-socfpga/archive/refs/tags/QPDS24.1_REL_GSRD_PR.zip
unzip QPDS24.1_REL_GSRD_PR.zip
mv ghrd-socfpga-QPDS24.1_REL_GSRD_PR/a10_soc_devkit_ghrd_pro a10_soc_devkit_ghrd
rm -rf  ghrd-socfpga-QPDS24.1_REL_GSRD_PR QPDS24.1_REL_GSRD_PR.zip
cd a10_soc_devkit_ghrd
make clean && make scrub_clean && rm -rf software
sed -i 's/HPS_BOOT_DEVICE .= .*/HPS_BOOT_DEVICE := NAND/g' Makefile
make generate_from_tcl
make rbf

Build U-Boot

Get U-Boot source code

cd $TOP_FOLDER/a10_soc_devkit_ghrd/
rm -rf software/bootloader
mkdir -p software/bootloader
cd software/bootloader
git clone https://github.com/altera-opensource/u-boot-socfpga
cd u-boot-socfpga
# comment out next line to use the latest U-Boot branch
# git checkout -b test-bootloader -t origin/socfpga_v2023.07

Convert hps.xml handoff file to include file to be used by the device tree:

cd $TOP_FOLDER/a10_soc_devkit_ghrd/software/bootloader/u-boot-socfpga
./arch/arm/mach-socfpga/qts-filter-a10.sh \
../../../hps_isw_handoff/hps.xml \
arch/arm/dts/socfpga_arria10_socdk_nand_handoff.h

Configure and build U-Boot:

cd $TOP_FOLDER/a10_soc_devkit_ghrd/software/bootloader/u-boot-socfpga
export CROSS_COMPILE=arm-none-linux-gnueabihf-
make socfpga_arria10_nand_defconfig
make -j 48

This will create the following files:

File	Description
spl/u-boot-splx4.sfp	Bootable image containing four identical SPL binaries, with the header required by BootROM
u-boot.img	U-Boot image

Create the FIT image with the FPGA programming files, used by SPL to configure FPGA:

cd $TOP_FOLDER/a10_soc_devkit_ghrd/software/bootloader/u-boot-socfpga
ln -s ../../../output_files/ghrd_10as066n2.core.rbf .
ln -s ../../../output_files/ghrd_10as066n2.periph.rbf .
tools/mkimage -E -f board/altera/arria10-socdk/fit_spl_fpga.its fit_spl_fpga.itb

This creates the file fit_spl_fpga.itb.

Create FIT image for the U-Boot:

cd $TOP_FOLDER/a10_soc_devkit_ghrd/software/bootloader/u-boot-socfpga
tools/mkimage -E -f board/altera/arria10-socdk/fit_uboot.its  fit_uboot.itb

This creates the file fit_uboot.itb.

Create FIT image for the Linux kernel and device tree:

cd $TOP_FOLDER/a10_soc_devkit_ghrd/software/bootloader/u-boot-socfpga
ln -s $LINUX_BIN/a9/Image .
ln -s $LINUX_BIN/a9/socfpga_arria10_socdk_nand.dtb .
tools/mkimage -f  board/altera/arria10-socdk/fit_kernel_nand.its kernel.itb

This creates the file fit_kernel.itb.

C. Build NAND Binaries

Create nand_bin folder and bring all the files:

cd $TOP_FOLDER/
rm -rf nand_bin && mkdir nand_bin && cd nand_bin
cp ../a10_soc_devkit_ghrd/software/bootloader/u-boot-socfpga/spl/u-boot-splx4.sfp .
cp ../a10_soc_devkit_ghrd/software/bootloader/u-boot-socfpga/fit_uboot.itb .
cp ../a10_soc_devkit_ghrd/software/bootloader/u-boot-socfpga/fit_spl_fpga.itb .
cp ../a10_soc_devkit_ghrd/software/bootloader/u-boot-socfpga/kernel.itb .

Prepare JFFS2 rootfs image for booting Linux from NAND:

cd $TOP_FOLDER/nand_bin
rm -rf rootfs
mkdir rootfs
cd rootfs
tar xf $LINUX_BIN/a9/core-image-minimal-arria10.tar.gz
rm -rf lib/modules
cd ..
mkfs.jffs2 -r rootfs -n -p --faketime --output=rootfs.jffs2 --squash -s 2048 -e 128KiB
rm -rf rootfs

At this point the following binaries are available in the $TOP_FOLDER/nand_bin:

File	Description
u-boot-splx4.sfp	Four SPL binaries, with BootROM header
fit_uboot.itb	U-Boot image
fit_spl_fpga.itb	FPGA configuration files
kernel.itb	Linux kerned and device tree
rootfs.jffs2	Linux rootfs

D. Boot

NAND Flash Layout:

Address	Size	File	Description
0x0000000	0x00100000	u-boot-splx4.sfp	Four SPL binaries, with BootROM header
0x0100000	0x00100000	fit_uboot.itb	U-Boot image
0x0200000	0x00100000	n/a	U-Boot environment
0x0300000	0x00F00000	fit_spl_fpga.itb	FPGA configuration files
0x1200000	0x00E00000	kernel.itb	Linux kerned and device tree
0x0200000	0x06000000	rootfs.jffs2	Linux rootfs

Program NAND flash with all the binaries, by doing the following:

Copy the binaries to the TFTP folder on your host machine
Run U-Boot from the debugger as shown in Arria 10 SoC - Run U-Boot from Debugger
Connnect your U-Boot to the network, and specify the IP address of you host machine:

setenv autoload no
dhcp
setenv serverip <your_server_ip>

In U-Boot, download binaries over TFTP, and write the to NAND:

nand erase clean 0x02000000 0x06000000; tftp ${loadaddr} rootfs.jffs2; nand write.trimffs ${loadaddr} 0x02000000 ${filesize}
nand erase 0x01200000 0x00E00000; tftp ${loadaddr} kernel.itb; nand write ${loadaddr} 0x01200000 ${filesize}
nand erase 0x00300000 0x00F00000; tftp ${loadaddr} fit_spl_fpga.itb; nand write ${loadaddr} 0x00300000 ${filesize}
nand erase 0x00100000 0x00100000; tftp ${loadaddr} fit_uboot.itb; nand write ${loadaddr} 0x00100000 ${filesize}
nand erase 0x00000000 0x00100000; tftp ${loadaddr} u-boot-splx4.sfp; nand write ${loadaddr} 0x00000000 ${filesize}

Power cycle the board - it will boot to Linux login. Use 'root' as username with no pasword:

FPGA: Early Release Succeeded.
FPGA: Checking FPGA configuration setting …
FPGA: Start to program peripheral/full bitstream …
FPGA: Early Release Succeeded.

U-Boot SPL 2021.07-16360-gee63370553-dirty (Dec 21 2021 - 21:31:38 -0600)
DDRCAL: Success
DDRCAL: Scrubbing ECC RAM (1024 MiB).
DDRCAL: SDRAM-ECC initialized success with 163 ms
FPGA: Checking FPGA configuration setting …
FPGA: Start to program core bitstream …
Full Configuration Succeeded.
FPGA: Enter user mode.
WDT:   Started with servicing (10s timeout)
Trying to boot from NAND

U-Boot 2021.07-16360-gee63370553-dirty (Dec 21 2021 - 21:31:38 -0600)socfpga_arria10

CPU:   Altera SoCFPGA Arria 10
BOOT:  NAND Flash (1.8V)
Model: SOCFPGA Arria10 Dev Kit
DRAM:  1 GiB
WDT:   Started with servicing (10s timeout)
NAND:  128 MiB
Loading Environment from NAND... *** Warning - bad CRC, using default environment

In:    serial
Out:   serial
Err:   serial
Model: SOCFPGA Arria10 Dev Kit
Net:   
Warning: ethernet@ff800000 (eth0) using random MAC address - 5a:c1:fc:4a:a1:51
eth0: ethernet@ff800000
Hit any key to stop autoboot:  0 

NAND read: device 0 offset 0x1200000, size 0x6e00000
size adjusted to 0x6d80000 (4 bad blocks)
 114819072 bytes read: OK
## Loading kernel from FIT Image at 02100000 …
   Using 'conf' configuration
   Trying 'kernel' kernel subimage
     Description:  Linux Kernel
     Created:      2021-12-22   3:31:53 UTC
     Type:         Kernel Image
     Compression:  uncompressed
     Data Start:   0x021000cc
     Data Size:    14366044 Bytes = 13.7 MiB
     Architecture: ARM
     OS:           Linux
     Load Address: 0x00008000
     Entry Point:  0x00008000
   Verifying Hash Integrity … OK
## Loading fdt from FIT Image at 02100000 …
   Using 'conf' configuration
   Trying 'fdt' fdt subimage
     Description:  Linux DTB
     Created:      2021-12-22   3:31:53 UTC
     Type:         Flat Device Tree
     Compression:  uncompressed
     Data Start:   0x02eb36c4
     Data Size:    25186 Bytes = 24.6 KiB
     Architecture: ARM
   Verifying Hash Integrity … OK
   Booting using the fdt blob at 0x2eb36c4
   Loading Kernel Image
   Loading Device Tree to 09ff6000, end 09fff261 … OK

Starting kernel …

Deasserting all peripheral resets
[    0.000000] Booting Linux on physical CPU 0x0
[    0.000000] Linux version 5.10.70-75443-gdcd92725a9dd-dirty (radu@linux-machine) (arm-none-linux-gnueabihf-gcc (GNU Toolchain for the A-profile Architecture 10.2-2020.11 (arm-10.16)) 10.2.1 20201103, GNU ld (GNU Toolchain for the A-profile Architecture 10.2-2020.11 (arm-10.16)) 2.35.1.20201028) #1 SMP Mon Dec 20 11:18:16 CST 2021
[    0.000000] CPU: ARMv7 Processor [414fc091] revision 1 (ARMv7), cr=10c5387d
[    0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
[    0.000000] OF: fdt: Machine model: Altera SOCFPGA Arria 10

…

udhcpc: broadcasting discover
[    6.953579] socfpga-dwmac ff800000.ethernet eth0: Link is Up - 1Gbps/Full - flow control off
[    6.962025] IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready
udhcpc: broadcasting discover
udhcpc: broadcasting discover
udhcpc: no lease, forking to background
done.
Starting syslogd/klogd: done

Poky (Yocto Project Reference Distro) 3.4.1 arria10 /dev/ttyS0

arria10 login: root
root@arria10:~#

Appendix - Building Linux Binaries

This section details how to build the Linux binaries, which are used in the boot examples above. Building Linux is beyond the scope of this page, and minimal instructions are included for reference only.

Prerequisites

A number of Linux packages are required to be installed in order to build the Linux kernel and rootfs. On the Ubuntu 18.04LTS machine where the instructions from this page were tested, the following command was used to install them:

sudo apt-get install gawk wget git-core diffstat unzip texinfo \
gcc-multilib  build-essential chrpath socat cpio python python3 \
python3-pip python3-pexpect  xz-utils debianutils iputils-ping \
python3-git python3-jinja2 libegl1-mesa libsdl1.2-dev  pylint3 xterm \
libncurses-dev gawk flex bison openssl libssl-dev

Prepare a folder where to put all the build binaries, used by the boot examples:

rm -rf linux-bin && mkdir linux-bin
export set LINUX_BIN=`pwd`/linux-bin
mkdir -p $LINUX_BIN/a9

Building Linux Kernel

This section presents how to build the Linux kernel used for the boot examples on this page. Refer to https://rocketboards.org/foswiki/Main/GettingStarted for complete instructions.

Prepare a top folder:

rm -rf linux && mkdir linux
export set LINUX_TOP=`pwd`/linux

Cyclone V and Arria 10

Download and setup the toolchain:

cd $LINUX_TOP
export ARCH=arm
export CROSS_COMPILE=arm-none-linux-gnueabihf-

Clone the Linux git tree to retrieve the code:

cd $LINUX_TOP
git clone https://github.com/altera-opensource/linux-socfpga linux-socfpga.a9
cd linux-socfpga.a9
# comment out next line to use the latest Linux kernel branch
# Please use Linux Kernel Branch socfpga-5.15.50-lts for Cyclone V
git checkout -b nanbield -t origin/socfpga-6.1.68-lts

Note that most Cyclone V SoC DevKits have a 512MB QSPI flash device, while the Linux kernel DTS assumes a 1Gb (128MB) one. If you have the standard 512MB one, change the file linux-socfpga/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts accordingly before building dtbs:

    partition@qspi-rootfs {
         /* 56MB for jffs2 data. */
         label = "Flash 0 jffs2 Filesystem";
         reg = <0x800000 0x3800000>;
      };

The above can be scripted with the following commands:

sed -i 's/120MB for jffs2 data/56MB for jffs2 data/g' arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
sed -i 's/<0x800000 0x7800000>;/<0x800000 0x3800000>;/g' arch/arm/boot/dts/socfpga_cyclone5_socdk.dts

Build the Linux kernel:

make socfpga_defconfig
make -j 48 zImage Image dtbs modules
make -j 48 modules_install INSTALL_MOD_PATH=modules_install
rm -rf modules_install/lib/modules/*/build
rm -rf modules_install/lib/modules/*/source

Link all the relevant files to $LINUX_BIN

ln -s $LINUX_TOP/linux-socfpga.a9/arch/arm/boot/zImage $LINUX_BIN/a9/
ln -s $LINUX_TOP/linux-socfpga.a9/arch/arm/boot/Image $LINUX_BIN/a9/
ln -s $LINUX_TOP/linux-socfpga.a9/arch/arm/boot/dts/socfpga_cyclone5_socdk.dtb $LINUX_BIN/a9/
ln -s $LINUX_TOP/linux-socfpga.a9/arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dtb $LINUX_BIN/a9/
ln -s $LINUX_TOP/linux-socfpga.a9/arch/arm/boot/dts/socfpga_arria10_socdk_qspi.dtb $LINUX_BIN/a9/
ln -s $LINUX_TOP/linux-socfpga.a9/arch/arm/boot/dts/socfpga_arria10_socdk_nand.dtb $LINUX_BIN/a9/
ln -s $LINUX_TOP/linux-socfpga.a9/modules_install/lib/modules $LINUX_BIN/a9/

The following items are copied in the $LINUX_BIN/a9 folder:

Item	Description
zImage	compressed kernel image
Image	uncompressed kernel image
socfpga_cyclone5_socdk.dtb	cyclone v device tree blob for both sdmmc and qspi boot
socfpga_arria10_socdk_sdmmc.dtb	arria 10 device tree blob for sdmmc boot
socfpga_arria10_socdk_qspi.dtb	arria 10 device tree blob for qspi boot
socfpga_arria10_socdk_nand.dtb	arria 10 device tree blob for nand boot
modules	kernel loadable modules

Building Yocto Rootfs

This section presents how to build the Linux rootfs using Yocto recipes. Note that the yocto recipes actually build everything, but are only interested in the rootfs.

First, make sure you have Yocto system requirements met: https://docs.yoctoproject.org/3.4.1/ref-manual/system-requirements.html#supported-linux-distributions.

The command to install the required packages on Ubuntu is:

sudo apt install gawk wget git diffstat unzip texinfo gcc build-essential chrpath \
socat cpio python3 python3-pip python3-pexpect xz-utils debianutils iputils-ping \
python3-git python3-jinja2 libegl1-mesa libsdl1.2-dev pylint3 xterm python3-subunit \
mesa-common-dev zstd liblz4-tool

Note: You can also use a Docker container to build the Yocto recipes, refer to https://rocketboards.org/foswiki/Documentation/DockerYoctoBuild for details. When using a Docker container, it does not matter what Linux distribution or packages you have installed on your host, as all dependencies are provided by the Docker container.

Prepare a top folder:

cd $LINUX_TOP
mkdir rootfs && cd rootfs
export set ROOTFS_TOP=`pwd`

Run the build instructions from the following sections, to obtain the following files in the $LINUX_BIN folder:

File	Description
a9/core-image-minimal-cyclone5.tar.gz	Cyclone V rootfs archive
a9/core-image-minimal-arria10.tar.gz	Arria 10 rootfs archive

Cyclone V

cd $ROOTFS_TOP
rm -rf cv && mkdir cv && cd cv
git clone -b kirkstone https://git.yoctoproject.org/poky
git clone -b kirkstone https://git.yoctoproject.org/meta-intel-fpga
source poky/oe-init-build-env ./build
echo 'MACHINE = "cyclone5"' >> conf/local.conf
echo 'BBLAYERS += " ${TOPDIR}/../meta-intel-fpga "' >> conf/bblayers.conf
# Uncomment next line to add more packages to the image
# echo 'CORE_IMAGE_EXTRA_INSTALL += "openssh gdbserver"' >> conf/local.conf
bitbake core-image-minimal
ln -s $ROOTFS_TOP/cv/build/tmp/deploy/images/cyclone5/core-image-minimal-cyclone5.tar.gz $LINUX_BIN/a9/

Arria 10

cd $ROOTFS_TOP
rm -rf a10 && mkdir a10 && cd a10
git clone -b nanbield https://git.yoctoproject.org/poky
git clone -b nanbield https://git.yoctoproject.org/meta-intel-fpga
source poky/oe-init-build-env ./build
echo 'MACHINE = "arria10"' >> conf/local.conf
echo 'BBLAYERS += " ${TOPDIR}/../meta-intel-fpga "' >> conf/bblayers.conf
# Uncomment next line to add more packages to the image
# echo 'CORE_IMAGE_EXTRA_INSTALL += "openssh gdbserver"' >> conf/local.conf
bitbake core-image-minimal
ln -s $ROOTFS_TOP/a10/build/tmp/deploy/images/arria10/core-image-minimal-arria10.tar.gz $LINUX_BIN/a9/

Appendix - Reducing Arria 10 Fabric Configuration Time

Arria 10 FPGA configuration is done in two steps:

Configuration of periphery: this allows HPS DDRAM to be brought up, and must do be done in SPL
Configuration of fabric: it configures the actual FPGA core fabric, and can be done from SPL or U-Boot

Warning: the periphery and fabric configuration files must come from the same Quartus compilation of a hardware project. Combining files from different projects or from different compilations of the same project is not supported.

Warning: the fabric cannot be configured from Linux. If you need to define or change the fabric behavior from Linux, you must use PR (partial reconfiguration).

The standard flow configures the Arria 10 FPGA Fabric from the SPL. However, this is a very slow process. This section shows a copuple of options for configuring the fabric from the U-Boot instead of SPL, which is significantly faster.

The examples show how to do it when booting from SD card. Similar commands can be used for the QSPI case.

Option #1 - Separate Configuration Files

In this option, we are moving the FPGA fabric configuration file out of FIT image, and keep it as a separate file.

1. Change the file board/altera/arria10-socdk/fit_spl_fpga.its to only configure the periphery, and not the fabric:

/dts-v1/;
/ {
   description = "FIT image with FPGA bistream";
   #address-cells = <1>;

   images {
      fpga-periph-1 {
         description = "FPGA peripheral bitstream";
         data = /incbin/("../../../ghrd_10as066n2.periph.rbf");
         type = "fpga";
         arch = "arm";
         compression = "none";
      };
   };

   configurations {
      default = "config-1";
      config-1 {
         description = "Boot with FPGA early IO release config";
         fpga = "fpga-periph-1";
      };
   };
};

2. Re-generate the corresponding .itb file - it will be much smaller since it will not include the FPGA fabric configuration file.

3. Store the ghrd_10as066n2.core.rbf file on the SD card, to be loaded from U-Boot

4. In the U-Boot boot flow, add the instructions to configure the FPGA fabric:

load mmc 0:1 ${loadaddr} ghrd_10as066n2.core.rbf
fpga load 0 ${loadaddr} ${filesize}

Option #2 - Combined Configuration File

In this option, we are keeping both configuration files in the same FIT image, but only apply the periphery one in the SPL. Then we are extrating the fabric file from the FIT file and using it in U-Boot to configure the fabric. The advantage is that we are keeping both files in a single place, which can aid in ensuring they are always in sync.

1. Change the file board/altera/arria10-socdk/fit_spl_fpga.its to contain the core configuration file, but not apply it in SPL:

/dts-v1/;
/ {
   description = "FIT image with FPGA bistream";
   #address-cells = <1>;

   images {
      fpga-periph-1 {
         description = "FPGA peripheral bitstream";
         data = /incbin/("../../../ghrd_10as066n2.periph.rbf");
         type = "fpga";
         arch = "arm";
         compression = "none";
      };

      fpga-core-1 {
         description = "FPGA core bitstream";
         data = /incbin/("../../../ghrd_10as066n2.core.rbf");
         type = "fpga";
         arch = "arm";
         compression = "none";
      };
   };

   configurations {
      default = "config-1";
      config-1 {
         description = "Boot with FPGA early IO release config";
         fpga = "fpga-periph-1"
      };
   };
};

2. In the U-Boot boot flow, add the instructions to load the FPGA fabric file from the FIT file, and configure the fabric with it:

setenv coreaddr 0x1000000
load mmc 0:1 ${loadaddr} fit_spl_fpga.itb
imxtract ${loadaddr} fpga-core-1 ${coreaddr}
fpga load 0 ${coreaddr} ${filesize}

Note the the coreaddr size must be chosen to that it does not interfere with other U-Boot components or already loaded boot items.

Appendix - Running U-Boot with the Debugger from Command Line

This section presents examples of how to run U-Boot with the Arm Development Studio from command line. This offers a simple and convenient way to run U-Boot and use it for example to program onboard flash.

Cyclone V SoC - Run U-Boot from Debugger

1. Use the binaries built for the Cyclone V SoC Boot from SD Card example:

cd cv_example.sdmmc

2. Create debugger script:

cat <<EOT > cv_soc_devkit_ghrd/software/bootloader/run-u-boot.ds
# initialize system
stop
wait 5s
reset
stop
wait 5s
set trust-ro-sections-for-opcodes off

# load and run SPL
loadfile u-boot-socfpga/spl/u-boot-spl 0x0
start
wait
restore u-boot-socfpga/spl/u-boot-spl-dtb.bin binary 0xffff0000
tbreak spl_boot_device
# ← stop script here if you need to debug SPL
continue
wait 60s

# load and run U-Boot
delete
loadfile u-boot-socfpga/u-boot
start 
wait
restore u-boot-socfpga/u-boot.dtb binary &_end
# tbreak relocate_code
# continue
# wait 60s
# symbol-file "\$sdir/u-boot-socfpga/u-boot" ((gd_t*)\$r9)->reloc_off
# thbreak board_init_r
# continue
# wait 60s
# ← stop script here if you need to debug U-Boot
continue
EOT

4. Run jtagconfig to determine the connection parameters:

~/intelFPGA_pro/22.1std/nios2eds/nios2_command_shell.sh jtagconfig
1) USB-BlasterII [3-3.1.3]
  4BA00477   SOCVHPS
  02D020DD   5CSEBA6(.|ES)/5CSEMA6/..

5. Run the debugger from command line, using the connection parameters reported above by jtagconfig, shown in red below:

cd cv_soc_devkit_ghrd/software/bootloader
~/intelFPGA_pro/22.1std/nios2eds/nios2_command_shell.sh \
/opt/arm/developmentstudio-2021.1/bin/armdbg  \
--cdb-entry="Intel SoC FPGA::Cyclone V SoC (Dual Core)::Bare Metal Debug::Bare Metal Debug::Debug Cortex-A9_0::USB-Blaster" \
--cdb-entry-param="rvi_address=USB-BlasterII on localhost [3-3.1.3]:USB-BlasterII 3-3.1.3" \
--continue_on_error=true \
--stop_on_connect=false \
-s run-u-boot.ds

6. The serial console will show SPL then U-Boot being run:

U-Boot SPL 2020.10-10892-gced41867be-dirty (Mar 16 2021 - 20:13:21 -0500)
DDRCAL: Scrubbing ECC RAM (1024 MiB).
DDRCAL: SDRAM-ECC initialized success with 579 ms

U-Boot 2020.10-10892-gced41867be-dirty (Mar 16 2021 - 20:13:21 -0500)
CPU:   Altera SoCFPGA Platform
FPGA:  Altera Cyclone V, SE/A6 or SX/C6 or ST/D6, version 0x0
BOOT:  SD/MMC Internal Transceiver (3.0V)
       Watchdog enabled
DRAM:  1 GiB
MMC:   dwmmc0@ff704000: 0
Loading Environment from MMC... Card did not respond to voltage select!
*** Warning - No block device, using default environment

In:    serial
Out:   serial
Err:   serial
Model: Altera SOCFPGA Cyclone V SoC Development Kit
Net:   
Warning: ethernet@ff702000 (eth0) using random MAC address - 9a:6b:16:ac:03:c1
eth0: ethernet@ff702000
Hit any key to stop autoboot:  0
=>

Arria 10 SoC - Run U-Boot from Debugger

1. Use the binaries built for the Arria 10 SoC Boot From SD Card example:

cd arria10_example.sdmmc

2. Create debugger script:

cat <<EOT > a10_soc_devkit_ghrd/software/bootloader/run-u-boot.ds

# initialize system
stop
wait 5s
reset
stop
wait 5s
set trust-ro-sections-for-opcodes off

# load spl and run up until the warm reset
restore u-boot-socfpga/spl/u-boot-spl-dtb.bin binary 0xFFE00000
symbol-file u-boot-socfpga/spl/u-boot-spl
set \$PC = \$ENTRYPOINT
thbreak *0x0
# ← stop script here if you need to debug first pass of SPL
continue
wait 60s

# load spl again and run up until spl_boot_device
restore u-boot-socfpga/spl/u-boot-spl-dtb.bin binary 0xFFE00000
symbol-file u-boot-socfpga/spl/u-boot-spl
set \$PC = \$ENTRYPOINT
thbreak *0x0
thbreak spl_boot_device
# ← stop script here if you need to debug second pass of SPL
continue
wait 60s

# load u-boot and run up to board_init_r
delete
loadfile u-boot-socfpga/u-boot
start 
wait
restore u-boot-socfpga/u-boot.dtb binary &_end
thbreak relocate_code
continue
wait 60s
symbol-file u-boot-socfpga/u-boot ((gd_t*)\$r9)->reloc_off
thbreak board_init_r
continue
wait 60s
# ← stop script here if you need to debug U-Boot
continue

EOT

Enable Quartus tools to be called from command line:

export QUARTUS_ROOTDIR=~/intelFPGA_pro/24.1/quartus/
export PATH=$QUARTUS_ROOTDIR/bin:$QUARTUS_ROOTDIR/linux64:$QUARTUS_ROOTDIR/../qsys/bin:$PATH

3. Configure the FPGA fabric: quartus_pgm -c 1 -m jtag -o "p;a10_soc_devkit_ghrd/output_files/ghrd_10as066n2.sof"

4. Run jtagconfig to determine the connection parameters: jtagconfig 1) USB-BlasterII [3-3.1.1] 02E050DD 10AS066H(1|2|3|3E2|4|4E2)/.. 4BA00477 SOCVHPS

5. Run the debugger from command line, using the connection parameters reported above by jtagconfig, shown in red below:

cd a10_soc_devkit_ghrd/software/bootloader
/opt/arm/developmentstudio-2021.1/bin/armdbg  \
--cdb-entry="Intel SoC FPGA::Arria 10 SoC::Bare Metal Debug::Bare Metal Debug::Debug Cortex-A9_0::USB-Blaster" \
--cdb-entry-param="rvi_address=USB-BlasterII on localhost [3-3.1.1]:USB-BlasterII 3-3.1.1" \
--continue_on_error=true \
--stop_on_connect=false \
-s run-u-boot.ds

6. The serial console will show SPL then U-Boot being run:

U-Boot SPL 2020.10-10892-gced41867be (Mar 16 2021 - 20:34:59 -0500)

U-Boot SPL 2020.10-10892-gced41867be (Mar 16 2021 - 20:34:59 -0500)
DDRCAL: Success
DDRCAL: Scrubbing ECC RAM (1024 MiB).
DDRCAL: SDRAM-ECC initialized success with 146 ms
WDT:   Started with servicing (30s timeout)

U-Boot 2020.10-10892-gced41867be (Mar 16 2021 - 20:34:59 -0500)socfpga_arria10

CPU:   Altera SoCFPGA Arria 10
BOOT:  SD/MMC External Transceiver (1.8V)
Model: Altera SOCFPGA Arria 10
DRAM:  1 GiB
WDT:   Started with servicing (30s timeout)
MMC:   dwmmc0@ff808000: 0
Loading Environment from MMC... *** Warning - bad CRC, using default environment

In:    serial
Out:   serial
Err:   serial
Model: Altera SOCFPGA Arria 10
Net:   
Warning: ethernet@ff800000 (eth0) using random MAC address - 4a:11:d5:65:72:c5
eth0: ethernet@ff800000
Hit any key to stop autoboot:  0 
=>

Appendix - Debugging U-Boot with Arm DS Eclipse

This section presents examples of how to debug U-Boot with from the Arm Development Studio Eclipse-based GUI.

Cyclone V SoC - Debugging U-Boot

Debugging SPL

1. Use the binaries built for the Cyclone V SoC Boot from SD Card example:

cd cv_example.sdmmc/software/bootloader

2. Start the Arm Development Studio Eclipse-based GUI:

~/intelFPGA/22.1std/nios2eds/nios2_command_shell.sh \
/opt/arm/developmentstudio-2021.1/bin/armds_ide -data workspace &

Note the above creates a new workspace in the cv_example.sdmmc/software/bootloader folder.

3. In Eclipse, Go to Run > Debug Configurations to open the Debug Configurations window.

4. In the Debug Configurations window

Select the Generic Arm C/C++ Application on the left panel and right-click it. From the menu that appears, select New Configuration.
Edit the Name field from "New_configuration" to something more descriptive, such as "Debug Cyclone V Bootloader"

5. In the Connection tab:

Go to Select target section and select Intel SoC FPGA > Cyclone V SoC (Dual Core) > Bare Metal Debug > Debug Cortex-A9_0
Select the Target Connection to be USB Blaster
Click the Bare Metal Debug > Connection Browse button and select your cable.

The Debug Configurations window should now look like this:

6. Go to the Debugger tab, and do the following

Select Connect Only
Check Execute debugger commands and enter the following commands:

# initialize system
stop
wait 5s
reset
stop
wait 5s
set trust-ro-sections-for-opcodes off

# load and start SPL
loadfile u-boot-socfpga/spl/u-boot-spl 0x0
start
wait
restore u-boot-socfpga/spl/u-boot-spl-dtb.bin binary 0xffff0000

Uncheck Host working directory > Use default and edit the value to add "/../" so that it looks in the parent folder of the workspace

The Debug Configurations window should now look like this:

7. Click the Debug button. Arm Development Studio will run the commands, therefore downloading the SPL to board and starting it. The Eclipse window should now look like this:

8. At this point you can use standard debug techniques to debug U-Boot SPL: viewing registers, variables, putting breakpoints, running step-by-step etc.

Debugging U-Boot

Debugging U-Boot is similiar with debugging SPL, just that a different script is used, as shown below:

# initialize system
stop
wait 5s
reset
stop
wait 5s
set trust-ro-sections-for-opcodes off

# load SPL and run up until spl_boot_device
loadfile u-boot-socfpga/spl/u-boot-spl 0x0
start
wait
restore u-boot-socfpga/spl/u-boot-spl.dtb binary &__bss_end
thbreak spl_boot_device
continue
wait 60s

# load and start U-Boot
delete
loadfile u-boot-socfpga/u-boot
start 
wait
restore u-boot-socfpga/u-boot.dtb binary &_end

# run until relocation, and adjust symbols accordingly
thbreak relocate_code
cont
wait 60s
symbol-file u-boot-socfpga/u-boot ((gd_t*)$r9)->reloc_off
thbreak board_init_r
continue
wait 60s

Arria 10 SoC - Debugging U-Boot

Important Note: U-Boot tries to initialize the SD card, so you need to have one installed in this example. It is preferrable to have an empty one, which will not try to boot Linux for example when you power up the board, which may interfere with debugging. If you do not have an empty SD card, you can power up the board without an SD card, then insert the SD card when you start debugging.

Debugging SPL

1. Use the binaries built for the Arria 10 SoC Boot From SD Card example:

cd arria10_example.sdmmc

Enable Quartus tools to be called from command line:

export QUARTUS_ROOTDIR=~/intelFPGA_pro/24.1/quartus/
export PATH=$QUARTUS_ROOTDIR/bin:$QUARTUS_ROOTDIR/linux64:$QUARTUS_ROOTDIR/../qsys/bin:$PATH

2. Configure the FPGA fabric: quartus_pgm -c 1 -m jtag -o "p;a10_soc_devkit_ghrd/output_files/ghrd_10as066n2.sof"

3. Go to the bootloder folder

cd a10_soc_devkit_ghrd/software/bootloader

4. Start the Arm Development Studio Eclipse-based GUI: /opt/arm/developmentstudio-2022.2/bin/armds_ide -data workspace & Note the above creates a new workspace in the arria10_example.sdmmc/software/bootloader folder.

5. In Eclipse, Go to Run > Debug Configurations to open the Debug Configurations window.

4. In the Debug Configurations window

Select the Generic Arm C/C++ Application on the left panel and right-click it. From the menu that appears, select New Configuration.
Edit the Name field from "New_configuration" to something more descriptive, such as "Debug Arria 10 Bootloader"

5. In the Connection tab:

Go to Select target section and select Intel SoC FPGA > Arria 10 > Bare Metal Debug > Debug Cortex-A9_0
Select the Target Connection to be Intel FPGA Download Cable
Click the Bare Metal Debug > Connection Browse button and select your cable.

The Debug Configurations window should now look like this:

6. Go to the Debugger tab, and do the following

Select Connect Only
Check Execute debugger commands and enter the following commands:

# initialize system
stop
wait 5s
reset
stop
wait 5s
set trust-ro-sections-for-opcodes off

# load and start SPL
restore u-boot-socfpga/spl/u-boot-spl-dtb.bin binary 0xFFE00000
symbol-file u-boot-socfpga/spl/u-boot-spl
set $PC = $ENTRYPOINT

Uncheck Host working directory > Use default and edit the value to add "/../" so that it looks in the parent folder of the workspace

The Debug Configurations window should now look like this:

7. Click the Debug button. Arm Development Studio will run the commands, therefore downloading the SPL to board and starting it. The Eclipse window should now look like this:

8. At this point you can use standard debug techniques to debug U-Boot SPL: viewing registers, variables, putting breakpoints, running step-by-step etc.

Important Note: On Arria 10, after a cold reset, the U-Boot SPL runs up to a point, early in the initialization process, then it issues a warm reset and it runs again from the beginning, with a slightly different flow. This is done in order to work around a specific hardware issue. Typically you want to focus on the 2nd time the SPL is ran, and you can do this by using the following script instead:

# initialize system
stop
wait 5s
reset
stop
wait 5s
set trust-ro-sections-for-opcodes off

# load SPL and run up until the warm reset
restore u-boot-socfpga/spl/u-boot-spl-dtb.bin binary 0xFFE00000
symbol-file u-boot-socfpga/spl/u-boot-spl
set $PC = $ENTRYPOINT
thbreak *0x0
continue
wait 60s

# load SPL again and start it
restore u-boot-socfpga/spl/u-boot-spl-dtb.bin binary 0xFFE00000
symbol-file u-boot-socfpga/spl/u-boot-spl
set $PC = $ENTRYPOINT

Debugging U-Boot

Debugging U-Boot is similiar with debugging SPL, just that a different script is used, as shown below:

# initialize system
stop
wait 5s
reset
stop
wait 5s
set trust-ro-sections-for-opcodes off

# load SPL and run up until the warm reset
restore u-boot-socfpga/spl/u-boot-spl-dtb.bin binary 0xFFE00000
symbol-file u-boot-socfpga/spl/u-boot-spl
set $PC = $ENTRYPOINT
thbreak *0x0
continue
wait 60s

# load SPL again and run up until spl_boot_device
restore u-boot-socfpga/spl/u-boot-spl-dtb.bin binary 0xFFE00000
symbol-file u-boot-socfpga/spl/u-boot-spl
set $PC = $ENTRYPOINT
thbreak spl_boot_device
continue
wait 60s

# load and start U-Boot
delete
loadfile u-boot-socfpga/u-boot
start 
wait
restore u-boot-socfpga/u-boot.dtb binary &_end

# run until relocation, and adjust symbols accordingly
thbreak relocate_code
cont
wait 60s
symbol-file u-boot-socfpga/u-boot ((gd_t*)$r9)->reloc_off
thbreak board_init_r
continue
wait 60s

Appendix - Customizing Arria 10 GHRD Recipes for Custom Board

Refer to this KDB link for more information: https://www.intel.com/content/www/us/en/support/programmable/articles/000090551.html

Page Revision History

Page Revision	Changes
Rev 46	Quartus Pro v24.1 Binary Release update for Arria 10
Rev 45	Quartus Pro v23.4 Binary Release update for Arria 10
Rev 43	Quartus Pro v23.3 Binary Release update for Arria 10
Rev 42	Quartus Pro v23.2 Binary Release update for Arria 10
Rev 40	Quartus Pro v23.1 Binary Release update for Arria 10
Rev 38	Added new section: Appendix - Customizing Arria 10 GHRD Recipes for Custom Board and Page Revision History
Rev 37	Quartus Pro v22.4 Binary Release update for Arria 10
Rev 32	Quartus Std v22.1 Release update for Cyclone V, replacement of qts-filter.sh to cv_bsp_generator.py
Rev 27	Quartus Pro v22.3 Binary Release update for Arria 10
Rev 23	Quartus Pro v22.2 Binary Release update for Arria 10
Rev 20	Quartus Pro v22.1 Binary Release update for Arria 10

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Building Bootloader for Cyclone V and Arria 10 Information abut latest bootloaders for Cortex-A9 based SoC FPGA devices

Introduction

U-Boot Branches

U-Boot Build Flows

Cyclone V SoC and Arria V SoC

Arria 10 SoC

U-Boot Examples

Prerequisites

Cyclone V SoC - Boot from SD Card

Cyclone V SoC - Boot from QSPI

Arria 10 SoC - Boot from SD Card

Arria 10 SoC - Boot from QSPI

Arria 10 SoC - Boot from NAND

Appendix - Building Linux Binaries

Prerequisites

Building Linux Kernel

Building Yocto Rootfs

Appendix - Reducing Arria 10 Fabric Configuration Time

Option #1 - Separate Configuration Files

Option #2 - Combined Configuration File

Appendix - Running U-Boot with the Debugger from Command Line

Cyclone V SoC - Run U-Boot from Debugger

Arria 10 SoC - Run U-Boot from Debugger

Appendix - Debugging U-Boot with Arm DS Eclipse

Cyclone V SoC - Debugging U-Boot

Arria 10 SoC - Debugging U-Boot

Appendix - Customizing Arria 10 GHRD Recipes for Custom Board

Page Revision History

Building Bootloader for Cyclone V and Arria 10
Information abut latest bootloaders for Cortex-A9 based SoC FPGA devices