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Stratix 10 SoC L-Tile GSRD
Golden System Reference Design for Stratix 10 SX SoC Development Kit L-Tile

06 April 2024 - 01:33 | Release 24.1 | | GHRD, GSRD, Golden System Reference Design, Linux, SoC, Stratix 10, U-Boot

Overview

The Stratix 10 SX SoC Development Kit H-Tile and Stratix 10 SX SoC Development Kit L-Tile are very similar boards, as documented at Intel Stratix 10 SX SoC Development Kit.

This page presents the full GSRD (Golden System Reference Design) provided for the L-Tile version, including prebuilt binaries, instructions on how to use it, and instructions on how to rebuild it.

For instructions on how to build the H-Tile version, refer to Stratix 10 SoC H-Tile GSRD.

Prerequisites

The following are required in order to be able to fully exercise the S10 GSRD:
  • Stratix 10 SoC Development Kit, production version (ordering code DK-SOC-1SSX-L-D)
    • 4GB DDR4 HILO memory card
    • SD/MMC HPS Daughtercard
    • SDM QSPI Bootcard(MT25QU02G)
    • Mini USB cable for serial output
    • Micro USB cable for on-board Intel FPGA Download Cable II
  • Micro SD card (4GB or greater)
  • Host PC with
    • Linux - Ubuntu 22.04 was used to create this page, other versions and distributions may work too
    • Serial terminal (for example Minicom on Linux and TeraTerm or PuTTY on Windows)
    • Micro SD card slot or Micro SD card writer/reader
    • Intel Quartus Prime Pro Edition
      • v24.1 for exercising the binaries
      • v24.1 for rebuilding the current GSRD version
  • Local Ethernet network, with DHCP server (will be used to provide IP address to the board)

Release Content

Intel FPGA HPS Embedded Software Release Notes

The Intel FPGA HPS Embedded Software release notes can be accessed from the following link: https://www.rocketboards.org/foswiki/Documentation/IntelFPGAHPSEmbeddedSoftwareRelease

Latest Binaries Release Content

Binaries for SD Card Boot

The release files are accessible at https://releases.rocketboards.org/2024.04/gsrd/s10_gsrd/.

To load the binaries in the development kit see Booting Linux Using Precompiled Binaries.

The source code is also included on the SD card in the Linux rootfs path /home/root:

File Description
linux-socfpga-v6.1.68-lts-src.tar.gz Source code for Linux kernel
u-boot-socfpga-v2023.10-src.tar.gz Source code for U-Boot
arm-trusted-firmware-v2.10-src.tar.gz Source code for Arm Trusted Firmware

Before downloading the hardware design please read the agreement in the link https://www.intel.com/content/www/us/en/programmable/downloads/software/license/lic-prog_lic.html

Binaries for NAND Boot

The release files are accessible at https://releases.rocketboards.org/2024.04/nand/s10_nand/.

To load the binaries in the development kit see Write NAND Binaries but use the pre-built binaries listed above instead of the ones built in that section.

Binaries for QSPI Boot

The release files are accessible at https://releases.rocketboards.org/2024.04/qspi/s10_qspi/.

Note: The binary release mentioned above uses JFFS2 format for Linux root filesystem, while current source code release uses UBIFS. It is reccomended to use the new UBIFS format.

Note: To boot from QSPI is needed to remove SD card memory as SD Card memory has higher precedence in the boot order.

Latest Source Code Release Contents - Branches and Commit IDs

Quartus Prime Pro v24.1 and the following software component versions are used to build the GSRD:

Component Location Branch Commit ID/Tag
GHRD https://github.com/altera-opensource/ghrd-socfpga master QPDS24.1_REL_GSRD_PR
Linux https://github.com/altera-opensource/linux-socfpga socfpga-6.1.68-lts QPDS24.1_REL_GSRD_PR
Arm Trusted Firmware https://github.com/arm-trusted-firmware socfpga_v2.10.0 QPDS24.1_REL_GSRD_PR
U-Boot https://github.com/altera-opensource/u-boot-socfpga socfpga_v2023.10 QPDS24.1_REL_GSRD_PR
Yocto Project https://git.yoctoproject.org/poky nanbield latest
Yocto Project: meta-intel-fpga https://git.yoctoproject.org/meta-intel-fpga nanbield latest
Yocto Project: meta-intel-fpga-refdes https://github.com/altera-opensource/meta-intel-fpga-refdes nanbield QPDS24.1_REL_GSRD_PR

GHRD Overview

The Golden Hardware Reference Design is an important part of the GSRD and consists of the following components:
  • Hard Processor System (HPS)
    • Quad Arm Cortex-A53 MPCore Processor
    • HPS Peripherals connected to Out-of-Box Experience (OOBE) Daughter Card:
      • Micro SD for HPS storage
      • EMAC
      • HPS JTAG debug
      • I2C
      • USB UART
      • USB 2.0 OTG
      • Two Push buttons and Three LEDs
  • Hard Memory Controller (HMC) for HPS External Memory Interface (EMIF)
  • FPGA Peripherals connected to Lightweight HPS-to-FPGA (LWH2F) AXI Bridge and JTAG to Avalon Master Bridge
    • Three user LED outputs
    • Four user DIP switch inputs
    • Four user push-button inputs
    • Interrupt Latency Counter
    • System ID
  • FPGA Peripherals connected to HPS-to-FPGA (H2F) AXI Bridge
    • 256KB of FPGA on-chip memory
  • JTAG to Avalon Master Bridges connected to:
    • FPGA-to-SDRAM 0/1/2 Interfaces
    • FPGA-to-HPS AXI Bridge

s10-ghrd.png

The GHRD allows hardware designers to access each peripheral in the FPGA portion of the SoC with System Console, through the JTAG master module. This signal-level access is independent of the driver readiness of each peripheral.

Cortex-A53 MPU Address Maps

This section presents the address maps as seen from the MPU (Cortex-A53) side.

HPS-to-FPGA Address Map

The MPU region provide windows of 4 GB into the FPGA slave address space. The lower 1.5 GB of this space is mapped to two separate addresses - firstly from 0x8000_0000 to 0xDFFF_FFFF and secondly from 0x20_0000_0000 to 0x20_5FFF_FFFF. The following table lists the offset of each peripheral from the HPS-to-FPGA bridge in the FPGA portion of the SoC.

Peripheral Address Offset Size (bytes) Attribute
onchip_memory2_0 0x0 256K On-chip RAM as scratch pad

Lightweight HPS-to-FPGA Address Map

The the memory map of system peripherals in the FPGA portion of the SoC as viewed by the MPU (Cortex-A53), which starts at the lightweight HPS-to-FPGA base address of 0xF900_0000, is listed in the following table.

Peripheral Address Offset Size (bytes) Attribute
sysid 0x0000_0000 8 Unique system ID
led_pio 0x0000_1080 16 LED outputs
button_pio 0x0000_1060 16 Push button inputs
dipsw_pio 0x0000_1070 16 DIP switch inputs
ILC 0x0000_1100 256 Interrupt latency counter (ILC)

JTAG Master Address Map

There are two JTAG master interfaces in the design, one for accessing non-secure peripherals in the FPGA fabric, and another for accessing secure peripheral in the HPS through the FPGA-to-HPS Interface.

The following table lists the address of each peripheral in the FPGA portion of the SoC, as seen through the non-secure JTAG master interface.

Peripheral Address Offset Size (bytes) Attribute
onchip_memory2_0 0x0004_0000 256K On-chip RAM
sysid 0x0000_0000 8 Unique system ID
led_pio 0x0000_1080 16 LED outputs
button_pio 0x0000_1060 16 Push button inputs
dipsw_pio 0x0000_1070 16 DIP switch inputs
ILC 0x0000_1100 256 Interrupt latency counter (ILC)

Interrupt Routing

The HPS exposes 64 interrupt inputs for the FPGA logic. The following table lists the interrupt connections from soft IP peripherals to the HPS interrupt input interface.
Peripheral Interrupt Number Attribute
dipsw_pio f2h_irq0[0] 4 DIP switch inputs
button_pio f2h_irq0[1] 4 Push button inputs
The interrupt sources are also connected to an interrupt latency counter (ILC) module in the system, which enables System Console to be aware of the interrupt status of each peripheral in the FPGA portion of the SoC.

Typical HPS Boot Flow

The GSRD boot flow includes the following stages:
  1. SDM
  2. U-Boot SPL
  3. ATF
  4. U-Boot
  5. Linux
  6. Application
s10 agilex hps boot flow.png

The following table presents a short description of the different boot stages:

Stage Description
SDM Secure Device Manager boots first
U-Boot SPL Configures IO, FPGA, brings up SDRAM
ATF Arm Trusted Firmware, provides SMC handler
U-Boot Loads Linux kernel
Linux Operating system
Application User application

For more information, please refer to Intel Stratix 10 SoC Boot User Guide and Intel Stratix 10 Hard Processor System Technical Reference Manual (Booting and Configuration chapter).

Running GSRD with Pre-Built Binaries

Booting Linux Using Precompiled Binaries

This section presents how to write the QSPI Flash and SD Card image files, configure the board and boot Linux.

Configuring Board

This section presents the necessary board settings in order to run the GSRD on the Intel FPGA Stratix 10 SoC development board.

s10-soc-board.png

First, confirm the following:
  • DDR4 memory card is installed on HPS HiLo memory socket
  • OOBE Daughter card is installed on HPS Daughter card socket
Then the board switches need to be configured as follows:

  • SW1: OFF-OFF-ON-ON-ON-ON-ON-ON
  • SW2: ON-ON-ON (SW2.4 is not connected)
  • SW3: All OFF
  • SW4: ON-OFF-OFF-ON

Writing JIC Image to QSPI Flash

The QSPI JIC image contains the FPGA configuration bitstream, and the U-Boot SPL.

1. Download and extract the image file: 

wget https://releases.rocketboards.org/2024.04/gsrd/s10_gsrd/ghrd_1sx280lu2f50e2vg.jic.tar.gz

tar xf ghrd_1sx280lu2f50e2vg.jic.tar.gz

2. Configure MSEL to JTAG:
  • SW2: ON-ON-ON (SW2.4 is not connected)

3. Power cycle the board

4. Write the image using the following commands: 

quartus_pgm -c 1 -m jtag -o "pvi;ghrd_1sx280lu2f50e2vg.jic"

5. Configure MSEL back to QSPI:
  • SW2: ON-OFF-OFF (SW2.4 is not connected)

Creating SD Card

This section explains how to create the SD card necessary to boot Linux, using the SD card image available with the pre-built Linux binaries package. Once the SD card has been created, insert the card into the SD slot of the Micro SD daughter card.

Creating SD Card on Linux

1. Download the SD card image from https://releases.rocketboards.org/2024.04/gsrd/s10_gsrd/sdimage.tar.gz and extract it.

The extacted file is named gsrd-console-image-stratix10.wic.

2. Determine the device associated with the SD card on the host by running the following command before and after inserting the card. 

$ cat /proc/partitions

Let's assume it is /dev/sdx.

3. Use dd utility to write the SD image to the SD card. 

$ sudo dd if=gsrd-console-image-stratix10.wic of=/dev/sdx bs=1M

Note we are using sudo to be able to write to the card.

4. Use sync utility to flush the changes to the SD card. 

$ sudo sync

Creating SD Card on Windows

1. Download the SD card image from https://releases.rocketboards.org/2024.04/gsrd/s10_gsrd/sdimage.tar.gz and extract it.

The extacted file is named gsrd-console-image-stratix10.wic.

2. Rename the wic file as sdcard.img

3. Use Win32DiskImager to write the image to the SD card. The tool can be downloaded from https://sourceforge.net/projects/win32diskimager/files/latest/download

win32diskimager.png

Configuring Serial Connection

The OOBE Daughter Card has a built-in FTDI USB to Serial converter chip that allows the host computer to see the board as a virtual serial port. Connect a mini-USB cable from the vertical USB connector on the HPS OOBE Daughtercard to an USB port on your host computer to use the serial port.

Ubuntu and other modern Linux distributions have built-in drivers for the FTDI USB to Serial converter chip, so no driver installation is necessary on those platforms. On Windows, you can get the drivers from this address if not already installed: https://www.ftdichip.com/Drivers/CDM/CDM21228_Setup.zip.

The serial communication parameters are:
  • Baud-rate: 115,200
  • Parity: none
  • Flow control: none
  • Stop bits: 1
On Windows, utilities such as TeraTerm and PuTTY can be used to connect to the board. They are easily configured from the tool menus.

On Linux, the minicom utility can be used. Here is how to configure it:

1. The virtual serial port is usually named /dev/ttyUSB0. In order to determine the device name associated with the virtual serial port on your host PC, please perform the following:
  • Use the following command to determine which USB serial devices are already installed: ls /dev/ttyUSB*
  • Connect mini USB cable from J7 to the PC. This will enable the PC to communicate with the board, even if the board is not powered yet.
  • Use the ls /dev/ttyUSB* command command again to determine which new USB serial device appeared.
2. Install minicom application on host PC, if not installed.
  • On Ubuntu, use sudo apt-get install minicom
3. Configure minicom. 

$ sudo minicom -s

Under Serial Port Setup choose the following:
  • Serial Device: /dev/ttyUSB0 (edit to match the system as necessary)
  • Bps/Par/Bits: 115200 8N1
  • Hardware Flow Control: No
  • Software Flow Control: No
  • Hit [ESC] to return to the main configuration menu

Select Save Setup as dfl to save the default setup. Then select Exit.

Booting Linux

This section presents how to boot Linux on the board. The required steps are:

1. Start serial terminal (when using Minicom it will connect using the selected settings, for others connect manually).

2. Power up the board.

3. U-Boot SPL is ran

4. U-Boot is ran

5. Linux boots.

6. Login using 'root' and no password. 

U-Boot SPL 2023.10 (Mar 21 2024 - 07:41:59 +0000)
Reset state: Cold
MPU         1000000 kHz
L3 main     400000 kHz
Main VCO    2000000 kHz
Per VCO     2000000 kHz
EOSC1       25000 kHz
HPS MMC     50000 kHz
UART        100000 kHz
DDR: 4096 MiB
SDRAM-ECC: Initialized success with 1175 ms
QSPI: Reference clock at 400000 kHz
WDT:   Started watchdog@ffd00200 with servicing every 1000ms (10s timeout)
denali-nand-dt nand@ffb90000: timeout while waiting for irq 0x2000
denali-nand-dt nand@ffb90000: reset not completed.
Trying to boot from MMC1
## Checking hash(es) for config board-4 … OK
## Checking hash(es) for Image atf … crc32+ OK
## Checking hash(es) for Image uboot … crc32+ OK
## Checking hash(es) for Image fdt-0 … crc32+ OK
NOTICE:  BL31: v2.10.0	(release):v2.3-6547-gafecefc0f
NOTICE:  BL31: Built : 08:52:03, Mar 21 2024

U-Boot 2023.10 (Mar 21 2024 - 07:41:59 +0000)socfpga_stratix10

CPU:   Intel FPGA SoCFPGA Platform (ARMv8 64bit Cortex-A53)
Model: SoCFPGA Stratix 10 SoCDK
DRAM:  2 GiB (effective 4 GiB)
Core:  27 devices, 22 uclasses, devicetree: separate
WDT:   Started watchdog@ffd00200 with servicing every 1000ms (10s timeout)
NAND:  denali-nand-dt nand@ffb90000: timeout while waiting for irq 0x2000
denali-nand-dt nand@ffb90000: reset not completed.
Failed to initialize Denali NAND controller. (error -5)
0 MiB
MMC:   dwmmc0@ff808000: 0
Loading Environment from FAT... Unable to read "uboot.env" from mmc0:1...
Loading Environment from UBI... denali-nand-dt nand@ffb90000: timeout while waiting for irq 0x2000
denali-nand-dt nand@ffb90000: reset not completed.
SF: Detected mt25qu02g with page size 256 Bytes, erase size 64 KiB, total 256 MiB
Could not find a valid device for ffb90000.nand.0
ubi0 error: ubi_read_volume_table: the layout volume was not found
ubi0 error: ubi_attach_mtd_dev: failed to attach mtd2, error -22
UBI error: cannot attach mtd2
UBI error: cannot initialize UBI, error -22
UBI init error 22
Please check, if the correct MTD partition is used (size big enough?)

** Cannot find mtd partition "root"
In:    serial0@ffc02000
Out:   serial0@ffc02000
Err:   serial0@ffc02000
Net:   
Warning: ethernet@ff800000 (eth0) using random MAC address - c2:a6:b4:37:9e:f2
eth0: ethernet@ff800000
Hit any key to stop autoboot:  0 
switch to partitions #0, OK
mmc0 is current device
Scanning mmc 0:1...
Found U-Boot script /boot.scr.uimg
2411 bytes read in 3 ms (784.2 KiB/s)
## Executing script at 05ff0000
crc32+ Trying to boot Linux from device mmc0
Found kernel in mmc0
17153139 bytes read in 810 ms (20.2 MiB/s)
## Loading kernel from FIT Image at 01000000 …
   Using 'board-4' configuration
   Verifying Hash Integrity … OK
   Trying 'kernel' kernel subimage
     Description:  Linux Kernel
     Type:         Kernel Image
     Compression:  lzma compressed
     Data Start:   0x010000dc
     Data Size:    9521379 Bytes = 9.1 MiB
     Architecture: AArch64
     OS:           Linux
     Load Address: 0x06000000
     Entry Point:  0x06000000
     Hash algo:    crc32
     Hash value:   474b072b
   Verifying Hash Integrity … crc32+ OK
## Loading fdt from FIT Image at 01000000 …
   Using 'board-4' configuration
   Verifying Hash Integrity … OK
   Trying 'fdt-4' fdt subimage
     Description:  socfpga_socdk_combined
     Type:         Flat Device Tree
     Compression:  uncompressed
     Data Start:   0x019253b0
     Data Size:    36985 Bytes = 36.1 KiB
     Architecture: AArch64
     Hash algo:    crc32
     Hash value:   9dd4ce96
   Verifying Hash Integrity … crc32+ OK
   Booting using the fdt blob at 0x19253b0
Working FDT set to 19253b0
## Loading fpga from FIT Image at 01000000 …
   Trying 'fpga-4' fpga subimage
     Description:  FPGA bitstream for GHRD
     Type:         FPGA Image
     Compression:  uncompressed
     Data Start:   0x01cc859c
     Data Size:    3747840 Bytes = 3.6 MiB
     Load Address: 0x0a000000
     Hash algo:    crc32
     Hash value:   27c307b7
   Verifying Hash Integrity … crc32+ OK
   Loading fpga from 0x01cc859c to 0x0a000000
….FPGA reconfiguration OK!
Enable FPGA bridges
   Programming full bitstream... OK
   Uncompressing Kernel Image
   Loading Device Tree to 000000007eac9000, end 000000007ead5078 … OK
Working FDT set to 7eac9000
SF: Detected mt25qu02g with page size 256 Bytes, erase size 64 KiB, total 256 MiB
Enabling QSPI at Linux DTB...
Working FDT set to 7eac9000
libfdt fdt_path_offset() returned FDT_ERR_NOTFOUND
libfdt fdt_path_offset() returned FDT_ERR_NOTFOUND
QSPI clock frequency updated
RSU: Firmware or flash content not supporting RSU
RSU: Firmware or flash content not supporting RSU
RSU: Firmware or flash content not supporting RSU
RSU: Firmware or flash content not supporting RSU

Starting kernel …

Deasserting all peripheral resets
[    0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034]
[    0.000000] Linux version 6.1.68-altera (oe-user@oe-host) (aarch64-poky-linux-gcc (GCC) 13.2.0, GNU ld (GNU Binutils) 2.41.0.20231213) #1 SMP PREEMPT Thu Mar 28 07:56:27 UTC 2024
[    0.000000] Machine model: SoCFPGA Stratix 10 SoCDK

…

[    9.929939] socfpga-dwmac ff804000.ethernet eth2: IEEE 1588-2008 Advanced Timestamp supported
[    9.938742] socfpga-dwmac ff804000.ethernet eth2: registered PTP clock
[    9.946645] socfpga-dwmac ff804000.ethernet eth2: configuring for phy/sgmii link mode
[   13.669944] socfpga-dwmac ff800000.ethernet eth0: Link is Up - 1Gbps/Full - flow control rx/tx
[   13.678651] IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready
[   14.013428] 8021q: 802.1Q VLAN Support v1.8

Poky (Yocto Project Reference Distro) 4.3.4 stratix10 ttyS0

stratix10 login: root

root@stratix10:~#

7. Run 'ifconfig' command to determine the IP of the board 

root@stratix10:~# ifconfig
eth0: flags=4163  mtu 1500
        inet 192.168.1.48  netmask 255.255.255.0  broadcast 192.168.1.255
        inet6 fe80::d429:5dff:fe20:d6f4  prefixlen 64  scopeid 0x20
        ether d6:29:5d:20:d6:f4  txqueuelen 1000  (Ethernet)
        RX packets 57  bytes 9330 (9.1 KiB)
        RX errors 0  dropped 0  overruns 0  frame 0
        TX packets 57  bytes 8062 (7.8 KiB)
        TX errors 0  dropped 0 overruns 0  carrier 0  collisions 0
        device interrupt 21  base 0x2000  

eth1: flags=4099  mtu 1500
        ether 8a:c5:fe:e4:b5:97  txqueuelen 1000  (Ethernet)
        RX packets 0  bytes 0 (0.0 B)
        RX errors 0  dropped 0  overruns 0  frame 0
        TX packets 0  bytes 0 (0.0 B)
        TX errors 0  dropped 0 overruns 0  carrier 0  collisions 0
        device interrupt 22  base 0xc000  

eth2: flags=4099  mtu 1500
        ether 66:fd:43:7f:bc:66  txqueuelen 1000  (Ethernet)
        RX packets 0  bytes 0 (0.0 B)
        RX errors 0  dropped 0  overruns 0  frame 0
        TX packets 0  bytes 0 (0.0 B)
        TX errors 0  dropped 0 overruns 0  carrier 0  collisions 0
        device interrupt 23  base 0xe000  

lo: flags=73  mtu 65536
        inet 127.0.0.1  netmask 255.0.0.0
        inet6 ::1  prefixlen 128  scopeid 0x10
        loop  txqueuelen 1000  (Local Loopback)
        RX packets 100  bytes 8440 (8.2 KiB)
        RX errors 0  dropped 0  overruns 0  frame 0
        TX packets 100  bytes 8440 (8.2 KiB)
        TX errors 0  dropped 0 overruns 0  carrier 0  collisions 0

Note: there are three network cards, one connected to the Ethernet port on the HPS Daughtercard, and two to the Ethernet ports on the DevKit, which are connected throgh SGMII.

Running Sample Linux Applications

The GSRD includes a number of sample Linux applications that help demonstrate some of the features of the platform:

  • Display Hello World message
  • Control LEDs
  • Detect interrupts from push buttons and DIP switches

The sample applications can be used as a starting point for users to write their own applications that interact with software IP through Linux drivers.

Prerequisites

1. Boot Linux on the target board as described in Booting Linux. You will not need to use the serial terminal if you plan on using ssh connection.

2. Connect to the board using one of the following options:

3. In serial console, or ssh client console, change current folder to be /home/root/intelFPGA. This is where the application binaries are stored. 

root@stratix10:~# cd /home/root/intelFPGA/

Display Hello World Message

Run the following command to display the Hello World message on the console: 

root@stratix10:~/intelFPGA# ./hello 
Hello SoC FPGA!

Exercise Soft PIO Driver for LED Control

The following LEDs are exercised:

User FPGA LED Number Corresponding Board LED
0 D21
1 D23
2 D25

Note: User FPGA LED #3 / D27 is quickly blinking, and cannot be controlled from software.

1. In order to blink an LED in a loop, with a specific delay in ms, run the following command: 

./blink <led_number> <delay_ms>
  • The led_number specifies the desired LED, and is a value between 0 and 3.
  • The delay_ms is a number that specifies the desired delay in ms between turning the LED on and off.

2. In order to turn an individual LED on or off, run the following command: 

./toggle <led_number> <state>
  • The led_number specifies the desired LED, and is a value between 0 and 3.
  • The state needs to be 0 to turn the LED off, and 1 to turn the LED on.

3. In order to scroll the FPGA LEDs with a specific delay, please run the following command: 

./scroll_client <delay>

The delay specifies the desired scrolling behavior:
  • delay > 0 - specify new scrolling delay in ms, and start scrolling
  • delay < 0 - stop scrolling
  • delay = 0 - display current scroll delay

Register Interrupts and Call Interrupt Service Routine

The following are exercised:
  • User FPGA DIP switches
    • SW3.1
    • SW3.2
    • SW3.3
    • SW3.4
  • User FPGA push buttons
    • 0: S4
    • 1: S5
    • 2: S6
    • 3: S7

In order to register an interrupt handler to a specific GPIO, you will first need to determine the GPIO number used.

1. Open the Linux Device Tree socfpga_stratix10_qse_pcie_sgmii_ghrd.dtsi file and look up the labels for the DIP switches and Push button GPIOs: 

    button_pio: gpio@f9001060 {
        compatible = "altr,pio-1.0";
        reg = <0xf9001060 0x10>;
        interrupt-parent = <&intc>; 
        interrupts = <0 18 4>;
        altr,gpio-bank-width = <4>;
        altr,interrupt-type = <2>;      
        altr,interrupt_type = <2>;
        #gpio-cells = <2>;
        gpio-controller;
    };

   dipsw_pio: gpio@f9001070 {
        compatible = "altr,pio-1.0";
        reg = <0xf9001070 0x10>;
        interrupt-parent = <&intc>; 
        interrupts = <0 17 4>;
        altr,gpio-bank-width = <4>;
        altr,interrupt-type = <3>;      
        altr,interrupt_type = <3>;
        #gpio-cells = <2>;
        gpio-controller;
    };

2. Run the following to determine the GPIO numbers for the DIP switches 

root@stratix10:~/intelFPGA#  grep -r "gpio@f9001070" /sys/class/gpio/gpiochip*/label 
/sys/class/gpio/gpiochip1928/label:/soc/gpio@f9001070

This means that the GPIOs 1928 .. 1931 are allocated to the DIP switches (there are 4 of them).

3. Run the followinig to determine the GPIO numbers for the pushbuttons 

root@stratix10:~/intelFPGA# grep -r "gpio@f9001060" /sys/class/gpio/gpiochip*/label
/sys/class/gpio/gpiochip1960/label:/soc/gpio@f9001060

This means that the GPIOs 1960 … 1963 are allocated to the push buttons (there are 4 of them).

4. Register interrupt for one of the dipswiches, using the appropriate GPIO number, as determined in a previous step: 

root@stratix10:~/intelFPGA# modprobe gpio_interrupt gpio_number=1928 intr_type=3
[ 1090.973366] Interrupt for GPIO:1928
[ 1090.973366]  registered

5. Toggle the dipswitch a few times, you will see messages from the interrupt handler 

[ 1096.537830] Interrupt happened at gpio:1928
[ 1096.547744] Interrupt happened at gpio:1928
[ 1098.736386] Interrupt happened at gpio:1928
[ 1098.740482] Interrupt happened at gpio:1928

6. Remove the driver 

root@stratix10:~/intelFPGA# rmmod gpio_interrupt

7. Register the pushbutton interrupt, using the appropriate GPIO number as determine on a previous step 

rroot@stratix10:~/intelFPGA# modprobe gpio_interrupt gpio_number=1960 intr_type=2
[ 1138.025297] Interrupt for GPIO:1960
[ 1138.025297]  registered

8. Push the pusbutton a few times, you will see interrupt handler messages 

[ 1141.672192] Interrupt happened at gpio:1960
[ 1142.110673] Interrupt happened at gpio:1960
[ 1142.499468] Interrupt happened at gpio:1960
[ 1142.884199] Interrupt happened at gpio:1960

9. Once done, remove the handler 

root@stratix10:~/intelFPGA# rmmod gpio_interrupt

Note: If you are on the ssh console, you will need to run the program dmesg after pressing the button in order to see the messages: 

root@stratix10:~/intelFPGA# dmesg

System Check Application

System check application provides a glance of system status of basic peripherals such as:

  • USB: USB device driver
  • Network IP (IPv4): Network IP address
  • HPS LEDs: HPS LED state
  • FPGA LEDs: FPGA LED state

Run the application by issuing the following command: 

root@stratix10:~/intelFPGA# ./syschk

The window will look as shown below - press 'q' to exit: 

                                                           ALTERA SYSTEM CHECK

IPv4 Address          : 192.168.1.48                           usb1                  : DWC OTG Controller

fpga_led2             : OFF                                    serial1@ffc02100      : disabled
hps_led2              : OFF                                    serial0@ffc02000      : okay
fpga_led0             : OFF
hps_led0              : OFF
fpga_led3             : OFF
fpga_led1             : OFF
hps_led1              : OFF

Connecting to Board Web Server and SSH Client

The GSRD includes a web server running on the target board that can be used to exercise some of the board features:

  • Turning LEDs ON and OFF
  • Scrolling LEDs in a sequence
  • Displaying the current status of the LEDs

The web page served by the web server also contains links to some relevant information on the Intel website.

Connect to Web Server

1. Boot Linux as described in Booting Linux.

2. Determine the IP address of the board using 'ifconfig' as shown above. Note there will be three network interfaces, you can use anyone which is connected to the local network and gets an IP from the DHCP server.

Note: There are instances where the DHCP have not assigned an IP to the board before the timeout happens, in which case you may check the IP address via the UART by running ifconfig.

3. Open a web browser on the host PC and type http:// on the address box, then type the IP of your board and hit Enter.

s10-gsrd-webserver.png

4. Scroll the webpage down to the section named Interacting with Stratix 10 SoC Development Kit.

s10-gsrd-webserver-interact.png

You will be able to perform the following actions:
  • See which LEDs are ON and which are off in the LED Status. Note that if the LEDs are setup to be scrolling, the displayed scrolling speed will not match the actual scrolling speed on the board.
  • Stop LEDs from scrolling, by clicking START and STOP buttons. The delay between LEDs turning ON and OFF is set in the LED Lightshow box.
  • Turn individual LEDs ON and OFF with the ON and OFF buttons. Note that this action is only available when the LED scrolling/lightshow is stopped.
  • Blink individual LEDs by typing a delay value in ms then clicking the corresponding BLINK button. Note that this action is only available when the LED scrolling/lightshow is stopped.

Connect Using SSH

1. The lower bottom of the web page presents instructions on how to connect to the board using an SSH connection.

s10-gsrd-webserver-ssh.png

2. If the SSH client is not installed on your host computer, you can install it by running the following command on CentOS: 

$ sudo yum install openssh-clients

or the following command on Ubuntu: 

$ sudo apt-get install openssh-client

3. Connect to the board, and run some commands, such as pwd, ls and uname to see Linux in action. 

radu@ubuntu:~$ ssh root@192.168.1.48
The authenticity of host '192.168.1.40 (192.168.1.40)' can't be established.
ECDSA key fingerprint is SHA256:fTZa4u/xMgLj7LB0YbeVG0qDumxD2yKCLPsObHqcVXQ.
Are you sure you want to continue connecting (yes/no/[fingerprint])? yes
Warning: Permanently added '192.168.1.40' (ECDSA) to the list of known hosts.
Last login: Wed Jan 25 22:12:53 2023
root@stratix10:~# pwd
/home/root
root@stratix10:~# ls
README                                 linux-socfpga-v5.15.70-lts-src.tar.gz
arm-trusted-firmware-v2.7-src.tar.gz   u-boot-socfpga-v2022.07-src.tar.gz
intelFPGA
root@stratix10:~# uname -a
Linux stratix10 5.15.70-altera #1 SMP PREEMPT Thu Dec 15 08:50:33 UTC 2022 aarch64 GNU/Linux
root@stratix10:~#

Building the GSRD

Important Note: The instructions from this section build the latest version of the GSRD. See Latest Source Release Contents for a list of used component versions.

Build Flow

The following diagram illustrates the full build flow for the GSRD based on source code from GitHub.

s10-gsrd-build-flow.svg

The current build flow creates a single boot image which is able to boot in different board configurations (either using OOBE or eMMC/NAND daughter card). For more information about how this single boot image is created, please refer to the following article: https://rocketboards.org/foswiki/Documentation/SingleImageBoot

Setting up Environment

Create a top folder for this example, as the rest of the commands assume this location: 

sudo rm -rf stratix10_gsrd
mkdir stratix10_gsrd
cd stratix10_gsrd
export TOP_FOLDER=$(pwd)

Download the compiler toolchain, add it to the PATH variable, to be used by the GHRD makefile to build the HPS Debug FSBL: 

cd $TOP_FOLDER
wget https://developer.arm.com/-/media/Files/downloads/gnu/11.2-2022.02/binrel/\
gcc-arm-11.2-2022.02-x86_64-aarch64-none-linux-gnu.tar.xz
tar xf gcc-arm-11.2-2022.02-x86_64-aarch64-none-linux-gnu.tar.xz
rm -f gcc-arm-11.2-2022.02-x86_64-aarch64-none-linux-gnu.tar.xz
export PATH=`pwd`/gcc-arm-11.2-2022.02-x86_64-aarch64-none-linux-gnu/bin:$PATH
export ARCH=arm64
export CROSS_COMPILE=aarch64-none-linux-gnu-

Enable Quartus tools to be called from command line: 

export QUARTUS_ROOTDIR=~/intelFPGA_pro/24.1/quartus/
export PATH=$QUARTUS_ROOTDIR/bin:$QUARTUS_ROOTDIR/linux64:$QUARTUS_ROOTDIR/../qsys/bin:$PATH

Building the Hardware Design 

cd $TOP_FOLDER
rm -rf ghrd-socfpga s10_soc_devkit_ghrd
git clone -b QPDS24.1_REL_GSRD_PR https://github.com/altera-opensource/ghrd-socfpga
mv ghrd-socfpga/s10_soc_devkit_ghrd .
rm -rf ghrd-socfpga
cd s10_soc_devkit_ghrd
make scrub_clean_all
make generate_from_tcl
make all
cd ..

The following files are created in $TOP_FOLDER/s10_soc_devkit_ghrd/output_files:
  • ghrd_1sx280lu2f50e2vg.sof - FPGA SOF file, without HPS FSBL
  • ghrd_1sx280lu2f50e2vg_hps_debug.sof - FPGA SOF, with HPS Debug FSBL
  • ghrd_1sx280lu2f50e2vg.pr_partition_0.rbf - PR bitsream for the baseline persona
  • alternate_persona.pr_partition_0.rbf - PR bitstream for the alternate persona

Building Core RBF

Create the Core RBF file to be used in the rootfs created by Yocto by using the HPS Debug SOF built by the GHRD makefile: 

cd $TOP_FOLDER
quartus_pfg -c s10_soc_devkit_ghrd/output_files/ghrd_1sx280lu2f50e2vg_hps_debug.sof \
  ghrd_1sx280lu2f50e2vg.jic \
  -o device=MT25QU02G \
  -o flash_loader=1SX280LU2 \
  -o mode=ASX4 \
  -o hps=1
rm ghrd_1sx280lu2f50e2vg.hps.jic

The following files will be created:
  • $TOP_FOLDER/ghrd_1sx280lu2f50e2vg.core.rbf - HPS First configuration bitstream, phase 2: FPGA fabric

Note we are also creating an HPS JIC file, but we are discarding it, as it has the HPS Debug FSBL, while the final image needs to have the U-Boot SPL created by the Yocto recipes.

Setting Up Yocto Build System

1. First, make sure you have Yocto system requirements met: https://docs.yoctoproject.org/3.4.1/ref-manual/system-requirements.html#supported-linux-distributions.

The command to install the required packages on Ubuntu 22.04 is: 

sudo apt-get update
sudo apt-get upgrade
sudo apt-get install openssh-server mc libgmp3-dev libmpc-dev gawk wget git diffstat unzip texinfo gcc \
build-essential chrpath socat cpio python3 python3-pip python3-pexpect xz-utils debianutils iputils-ping \
python3-git python3-jinja2 libegl1-mesa libsdl1.2-dev pylint3 xterm python3-subunit mesa-common-dev zstd \
liblz4-tool git fakeroot build-essential ncurses-dev xz-utils libssl-dev bc flex libelf-dev bison xinetd \
tftpd tftp nfs-kernel-server libncurses5 libc6-i386 libstdc++6:i386 libgcc++1:i386 lib32z1 \
device-tree-compiler curl mtd-utils u-boot-tools net-tools swig -y

On Ubuntu 20.04 you will also need to point the /bin/sh to /bin/bash, as the default is a link to /bin/dash: 

 sudo ln -sf /bin/bash /bin/sh

Note: You can also use a Docker container to build the Yocto recipes, refer to https://rocketboards.org/foswiki/Documentation/DockerYoctoBuild for details. When using a Docker container, it does not matter what Linux distribution or packages you have installed on your host, as all dependencies are provided by the Docker container.

2. Clone the Yocto script and prepare the build: 
cd $TOP_FOLDER
rm -rf gsrd_socfpga
git clone -b nanbield https://github.com/altera-opensource/gsrd_socfpga
cd gsrd_socfpga
. stratix10-gsrd-build.sh
build_setup

Note: Run the following commands to set up again the yocto build environments, if you closed the current window (for example when rebooting the Linux host) and want to resume the next steps: 

cd $TOP_FOLDER/gsrd_socfpga
. ./poky/oe-init-build-env stratix10-gsrd-rootfs/

Customize Yocto Build

1. Copy the rebuilt files to $WORKSPACE/meta-intel-fpga-refdes/recipes-bsp/ghrd/files using the following names, as expected by the yocto recipes:
  • stratix10_gsrd_ghrd.core.rbf
  • stratix10_pr_persona0.rbf
  • stratix10_pr_persona1.rbf
  • stratix10_nand_ghrd.core.rbf: not applicable, as we have not rebuilt the NAND version
This can be accomplished using the following instructions: 
GHRD_LOC=$WORKSPACE/meta-intel-fpga-refdes/recipes-bsp/ghrd/files
CORE_RBF=$GHRD_LOC/stratix10_gsrd_ghrd.core.rbf
PER0_RBF=$GHRD_LOC/stratix10_pr_persona0.rbf 
PER1_RBF=$GHRD_LOC/stratix10_pr_persona1.rbf
cp $TOP_FOLDER/ghrd_1sx280lu2f50e2vg.core.rbf $CORE_RBF
cp $TOP_FOLDER/s10_soc_devkit_ghrd/output_files/ghrd_1sx280lu2f50e2vg.pr_partition_0.rbf $PER0_RBF
cp $TOP_FOLDER/s10_soc_devkit_ghrd/output_files/alternate_persona.pr_partition_0.rbf $PER1_RBF

2. Update the Yocto recipe at $WORKSPACE/meta-intel-fpga-refdes/recipes-bsp/ghrd/hw-ref-design.bb to change the SRC_URI:stratix10 from the orginal value: 
SRC_URI:stratix10 ?= "\
      ${GHRD_REPO}/stratix10_gsrd_${ARM64_GHRD_CORE_RBF};name=stratix10_gsrd_core \
      ${GHRD_REPO}/stratix10_nand_${ARM64_GHRD_CORE_RBF};name=stratix10_nand_core \
      ${GHRD_REPO}/stratix10_pr_persona0.rbf;name=stratix10_pr_persona0 \
      ${GHRD_REPO}/stratix10_pr_persona1.rbf;name=stratix10_pr_persona1 \
      "
to be: 
SRC_URI:stratix10 ?= "\
      file://stratix10_gsrd_ghrd.core.rbf \
      ${GHRD_REPO}/stratix10_nand_${ARM64_GHRD_CORE_RBF};name=stratix10_nand_core \
      file://stratix10_pr_persona0.rbf \
      file://stratix10_pr_persona1.rbf \
      "
using the following commands from the console: 
OLD_CORE_URI="\${GHRD_REPO}\/stratix10_gsrd_\${ARM64_GHRD_CORE_RBF};name=stratix10_gsrd_core"
NEW_CORE_URI="file:\/\/stratix10_gsrd_ghrd.core.rbf"
OLD_PER0_URI="\${GHRD_REPO}\/stratix10_pr_persona0.rbf;name=stratix10_pr_persona0"
NEW_PER0_URI="file:\/\/stratix10_pr_persona0.rbf"
OLD_PER1_URI="\${GHRD_REPO}\/stratix10_pr_persona1.rbf;name=stratix10_pr_persona1"
NEW_PER1_URI="file:\/\/stratix10_pr_persona1.rbf"
RECIPE=$WORKSPACE/meta-intel-fpga-refdes/recipes-bsp/ghrd/hw-ref-design.bb
sed -i "s/$OLD_CORE_URI/$NEW_CORE_URI/g" $RECIPE
sed -i "s/$OLD_PER0_URI/$NEW_PER0_URI/g" $RECIPE
sed -i "s/$OLD_PER1_URI/$NEW_PER1_URI/g" $RECIPE
Note we have left the NAND file alone, that will be downloaded from rocketboards.

3. Update the same Yocto recipe to change the SHA checksums for the new files: 
SRC_URI[stratix10_gsrd_core.sha256sum] = "ea26a77ebc1b3141193de6dd32e22f332785e05c956de85118c3790392141d3c"
SRC_URI[stratix10_nand_core.sha256sum] = "d782c05085f8f13cb792b687fd002773e0897e4d7ecf5451994b1823d62cdc92"
SRC_URI[stratix10_pr_persona0.sha256sum] = "60af20604f8756b251d3bff23ceaf8c4edec6d37cf4558ed763e1e311ab4c81e"
SRC_URI[stratix10_pr_persona1.sha256sum] = "c555e432574431ec0d2596fe7dc3f4ace86899add91599023d26127a9d78293b"
to the new values using the following commands: 
CORE_SHA=$(sha256sum $CORE_RBF | cut -f1 -d" ")
PER0_SHA=$(sha256sum $PER0_RBF | cut -f1 -d" ")
PER1_SHA=$(sha256sum $PER1_RBF | cut -f1 -d" ")
OLD_CORE_SHA="SRC_URI\[stratix10_gsrd_core\.sha256sum\] = .*"
NEW_CORE_SHA="SRC_URI[stratix10_gsrd_core.sha256sum] =  \"$CORE_SHA\""
OLD_PER0_SHA="SRC_URI\[stratix10_pr_persona0\.sha256sum\] = .*"
NEW_PER0_SHA="SRC_URI[stratix10_pr_persona0.sha256sum] =  \"$PER0_SHA\""
OLD_PER1_SHA="SRC_URI\[stratix10_pr_persona1\.sha256sum\] = .*"
NEW_PER1_SHA="SRC_URI[stratix10_pr_persona1.sha256sum] =  \"$PER1_SHA\""
sed -i "s/$OLD_CORE_SHA/$NEW_CORE_SHA/g" $RECIPE
sed -i "s/$OLD_PER0_SHA/$NEW_PER0_SHA/g" $RECIPE
sed -i "s/$OLD_PER1_SHA/$NEW_PER1_SHA/g" $RECIPE

4. Optionally change the following files in $WORKSPACE/meta-intel-fpga-refdes/recipes-bsp/u-boot/files/:

5. Optionally change the following file in $WORKSPACE/meta-intel-fpga-refdes/recipes-kernel/linux/linux-socfpga-lts:
  • fit_kernel_stratix10.its - its file for creating the kernel.itb image, containing by default:
    • Kernel
    • Device trees for SD and NAND board configurations
    • Core RBF files for SD and NAND board configurations
    • Board configurations for SD and NAND cases

Build Yocto

Build Yocto: 
bitbake_image

Gather files: 
package

Once the build is completed successfully, you will see the following two folders are created:

The two most relevant files created in the $TOP_FOLDER/gsrd_socfpga/stratix10-gsrd-images folder are:

File Description
sdimage.tar.gz SD Card Image
u-boot-stratix10-socdk-gsrd-atf/u-boot-spl-dtb.hex U-Boot SPL Hex file

Building QSPI Flash Image

The QSPI image will contain the FPGA configuration data and the HPS FSBL and it can be built using the following command: 

cd $TOP_FOLDER
quartus_pfg -c s10_soc_devkit_ghrd/output_files/ghrd_1sx280lu2f50e2vg.sof \
  ghrd_1sx280lu2f50e2vg.jic \
  -o device=MT25QU02G \
  -o flash_loader=1SX280LU2 \
  -o hps_path=gsrd_socfpga/stratix10-gsrd-images/u-boot-stratix10-socdk-gsrd-atf/u-boot-spl-dtb.hex \
  -o mode=ASX4 \
  -o hps=1

The following files will be created:
  • $TOP_FOLDER/ghrd_1sx280lu2f50e2vg.hps.jic - Flash image for HPS First configuration bitstream, phase 1: HPS and DDR
  • $TOP_FOLDER/ghrd_1sx280lu2f50e2vg.core.rbf - HPS First configuration bitstream, phase 2: FPGA fabric. We already have the same file on the SD card.

Booting from QSPI

This section presents how to boot the Stratix 10 SoC from QSPI, using the rebuilt GSRD binaries.

The same binaries as when booting from SD card can be used to boot from QSPI, because:
  • The QSPI resides on the DevKit board, and not on the HPS daughtercard, so there are no board changes:
    • The same GHRD configuration can be used
    • The same U-Boot devce tree can be used
    • The same Linux device tree can be used
  • U-Boot uses distroboot, which will try first booting from SD/MMC, then from QSPI, then from NAND, so the same U-Boot can be used.

Note: As the QSPI has a much smaller size than the SD card (256MB vs 2GB) the rootfs is smaller, and less functionality is provided. The purpose of this section is just to show Linux booting.

Note: The HPS speed for accessing SDM QSPI is limited to ~4MB/s. It is up to you to decide whether this level of performance is sufficient for your application. If not, it is recommended you use an SD card or eMMC device to store the HPS components such as the rootfs. Note that the QSPI speed limitation does not apply when SDM accesses the QSPI, it is just for HPS accessing SDM QSPI.

QSPI Flash Layout

MTD Partition UBI Volume Volume Name Type Image/File Size
0 (qspi_uboot) N/A N/A RAW bitstream (FPGA image, SDM firmware) 64MB
N/A N/A RAW u-boot.itb 2MB
1 (qspi_root) 0 env UBI u-boot.env root.ubi 256KB
1 script UBI u-boot.scr 128KB
2 kernel UBI kernel.itb 24MB
3 dtb UBI kernel.dtb 256KB
4 rootfs UBIFS rootfs.ubifs 160MB

Creating the QSPI Flash Image

1. Create a folder to contain all the qspi binaries, and create symlinks to actual location for all files: 

cd $TOP_FOLDER
rm -rf qspi-boot && mkdir qspi-boot && cd qspi-boot
ln -s $TOP_FOLDER/s10_soc_devkit_ghrd/output_files/ghrd_1sx280lu2f50e2vg.sof fpga.sof
ln -s $TOP_FOLDER/gsrd_socfpga/stratix10-gsrd-images/u-boot-stratix10-socdk-gsrd-atf/u-boot-spl-dtb.hex spl.hex
ln -s $TOP_FOLDER/gsrd_socfpga/stratix10-gsrd-images/u-boot-stratix10-socdk-gsrd-atf/boot.scr.uimg .
ln -s $TOP_FOLDER/gsrd_socfpga/stratix10-gsrd-images/kernel.itb .
ln -s $TOP_FOLDER/gsrd_socfpga/stratix10-gsrd-images/console-image-minimal-stratix10_nor.ubifs rootfs.ubifs

2. Create U-Boot image: 

cd $TOP_FOLDER/qspi-boot
cp $TOP_FOLDER/gsrd_socfpga/stratix10-gsrd-images/u-boot-stratix10-socdk-gsrd-atf/u-boot.itb .
uboot_part_size=2*1024*1024
uboot_size=`wc -c < u-boot.itb`
uboot_pad="$((uboot_part_size-uboot_size))"
truncate -s +$uboot_pad u-boot.itb
mv u-boot.itb u-boot.bin

4. Create hps.ubi file: 

cd $TOP_FOLDER/qspi-boot
cat <ubinize.cfg
[env]
mode=ubi
vol_id=0
vol_name=env
vol_size=256KiB
vol_type=dynamic

[script]
mode=ubi
image=boot.scr.uimg
vol_id=1
vol_name=script
vol_size=128KiB 
vol_type=dynamic

[kernel]
mode=ubi
image=kernel.itb
vol_id=2
vol_name=kernel
vol_size=24MiB
vol_type=dynamic

[dtb]
mode=ubi
vol_id=3    
vol_name=dtb   
vol_size=256KiB 
vol_type=dynamic

[rootfs]
mode=ubi
image=rootfs.ubifs
vol_id=4
vol_name=rootfs
vol_type=dynamic
vol_size=160MiB
vol_flag=autoresize

EOT
ubinize -o root.ubi -p 65536 -m 1 -s 1 ubinize.cfg
ln -s root.ubi hps.bin

5. Create the QSPI image using the provided Quartus Programming File Generator (PFG) file: 

cd $TOP_FOLDER/qspi-boot
wget https://rocketboards.org/foswiki/pub/Documentation/Stratix10SoCGSRD/flash_image_qspi.pfg
quartus_pfg -c flash_image_qspi.pfg

The following files will be generated:
  • $TOP_FOLDER/qspi-boot/flash_image.hps.jic - JIC QSPI flash image
  • $TOP_FOLDER/qspi-boot/s10_flash_image.core.rbf - fabric configuration file, already generated previously with the debug HPS FSBL

Creating the Programming File Generator File

This section presents how to manually re-create the PFG file provided at https://releases.rocketboards.org/2024.04/qspi/s10_qspi/flash_image_qspi.pfg

1. Start Quartus Programming File Generator GUI: 

cd $TOP_FOLDER/qspi-boot
qpfgw &

2. In PFG Output Files tab:
  • Select Device Family as "Stratix 10"
  • Select Configuration Mode as "Active Serial x4"
  • Edit Name as "flash_image"
  • Check Raw Binary File for HPS Core Configuration (.rbf) option
  • Check the following sub-options:
    • Check JTAG Indirect Configuration File (.jic)
    • Check Memory Map File (.map)

s10-qspi-boot-output-files.png

3. In PFG Input Files tab:
  • Click Add Bitstream", then browse to "fpga.sof" link, and add click *Open to add it.
  • Click Bitstream_1>fpga.sof then click Properties the click HPS Bootloader, browse to "spl.hex" then click Open to add it.
    Note: By the time the fpga.sof file is read the following error is displayed, this was addressed by adding the spl.hex file to the Bitstream:
    File fpga.sof is incomplete- HPS is present but bootloader information is missing.
  • Click Add Raw Data then change the extension filter to .bin then browse to "u-boot.bin" and click Open to add it.
  • Click on the "u-boot.bin" then click "*Properties*" then select Bit swap option to "On"
  • Repeat the above 2 steps for the following file:
    • hps.bin

The Input Files tab will now look something like this:

s10-qspi-boot-input-files.png

4. In the PFG Configuration Device tab:
  • Click Add Device, select the Micron MT25QU02G device then click Add
  • Click the MT25QU02G device, then click Add Partition, select the options as following then click OK:
s10-qspi-boot-add-bitstream-partition.png
  • Click the MT25QU02G device, then click Add Partition, select the options as following then click OK:
s10-qspi-boot-add-u-boot-partition.png
  • Repeat the above step for the rest of binary files, choosing the following offsets:
    • hps: 0x04200000
  • Click Flash Loader > Select then browse to the device used on the devkit then click OK:
s10-qspi-boot-flash-loader.png

The Configuration Device tab will now look something like this:

s10-qspi-boot-configuration-device.png

3. Go to File > Save As and save the configuration file as "s10_flash_image_qspi.pfg".

4. [Optional] Open the file "s10_flash_image_qspi.pfg" with a text editor and change absolute paths to relative paths.

The file will look like this:
<pfg version="1">
<settings custom_db_dir="./" mode="ASX4"/>
<output_files>
<output_file name="flash_image" hps="1" directory="./" type="PERIPH_JIC">
<file_options/>
<secondary_file type="MAP" name="flash_image_jic">
<file_options/>
</secondary_file>
<flash_device_id>Flash_Device_1</flash_device_id>
</output_file>
</output_files>
<bitstreams>
<bitstream id="Bitstream_1">
<path signing="OFF" finalize_encryption="0" hps_path="spl.hex">fpga.sof</path>
</bitstream>
</bitstreams>
<raw_files>
<raw_file bitswap="1" type="RBF" id="Raw_File_1">u-boot.bin</raw_file>
<raw_file bitswap="1" type="RBF" id="Raw_File_2">hps.bin</raw_file>
</raw_files>
<flash_devices>
<flash_device type="MT25QU02G" id="Flash_Device_1">
<partition reserved="1" fixed_s_addr="1" s_addr="0x00000000" e_addr="0x000FFFFF" fixed_e_addr="1" id="BOOT_INFO" size="0"/>
<partition reserved="0" fixed_s_addr="0" s_addr="auto" e_addr="auto" fixed_e_addr="0" id="P1" size="0"/>
<partition reserved="0" fixed_s_addr="0" s_addr="0x04000000" e_addr="auto" fixed_e_addr="0" id="u-boot" size="0"/>
<partition reserved="0" fixed_s_addr="0" s_addr="0x04200000" e_addr="auto" fixed_e_addr="0" id="hps" size="0"/>
</flash_device>
<flash_loader>1SX280LU2</flash_loader>
</flash_devices>
<assignments>
<assignment page="0" partition_id="P1">
<bitstream_id>Bitstream_1</bitstream_id>
</assignment>
<assignment page="0" partition_id="u-boot">
<raw_file_id>Raw_File_1</raw_file_id>
</assignment>
<assignment page="0" partition_id="hps">
<raw_file_id>Raw_File_2</raw_file_id>
</assignment>
</assignments>
</pfg>

Writing the QSPI Flash Image

1. Configure MSEL to JTAG:
  • SW2: ON-ON-ON (SW2.4 is not connected)

2. Power cycle the board

3. Write the image using the following commands: 

quartus_pgm -c 1 -m jtag -o "pvi;flash_image.hps.jic"

Booting Linux

1. Configure MSEL back to QSPI:
  • SW2: ON-OFF-OFF (SW2.4 is not connected)

2. Important! Remove SD card, to confirm Linux is booting without it.

3. Power cycle. Board will boot up to Linux prompt, where you can login as 'root' without a password: 

U-Boot SPL 2023.10 (Mar 21 2024 - 07:41:59 +0000)
Reset state: Cold
MPU         1000000 kHz
L3 main     400000 kHz
Main VCO    2000000 kHz
Per VCO     2000000 kHz
EOSC1       25000 kHz
HPS MMC     50000 kHz
UART        100000 kHz
DDR: 4096 MiB
SDRAM-ECC: Initialized success with 1175 ms
QSPI: Reference clock at 400000 kHz
WDT:   Started watchdog@ffd00200 with servicing every 1000ms (10s timeout)
denali-nand-dt nand@ffb90000: timeout while waiting for irq 0x2000
denali-nand-dt nand@ffb90000: reset not completed.
Trying to boot from MMC1
Partition 1 invalid on device 0
spl_register_fat_device: fat register err - -1
spl_load_image_fat: error reading image u-boot.itb, err - -1
Trying to boot from SPI
## Checking hash(es) for config board-4 … OK
## Checking hash(es) for Image atf … crc32+ OK
## Checking hash(es) for Image uboot … crc32+ OK
## Checking hash(es) for Image fdt-0 … crc32+ OK
NOTICE:  BL31: v2.10.0	(release):v2.3-6547-gafecefc0f
NOTICE:  BL31: Built : 08:52:03, Mar 21 2024

U-Boot 2023.10 (Mar 21 2024 - 07:41:59 +0000)socfpga_stratix10

CPU:   Intel FPGA SoCFPGA Platform (ARMv8 64bit Cortex-A53)
Model: SoCFPGA Stratix 10 SoCDK
DRAM:  2 GiB (effective 4 GiB)
Core:  27 devices, 22 uclasses, devicetree: separate
WDT:   Started watchdog@ffd00200 with servicing every 1000ms (10s timeout)
NAND:  denali-nand-dt nand@ffb90000: timeout while waiting for irq 0x2000
denali-nand-dt nand@ffb90000: reset not completed.
Failed to initialize Denali NAND controller. (error -5)
0 MiB
MMC:   dwmmc0@ff808000: 0
Loading Environment from FAT... ** No partition table - mmc 0 **
Loading Environment from UBI... denali-nand-dt nand@ffb90000: timeout while waiting for irq 0x2000
denali-nand-dt nand@ffb90000: reset not completed.
SF: Detected mt25qu02g with page size 256 Bytes, erase size 64 KiB, total 256 MiB
Could not find a valid device for ffb90000.nand.0
Read 8192 bytes from volume env to 000000007fae2500
*** Warning - bad CRC, using default environment

In:    serial0@ffc02000
Out:   serial0@ffc02000
Err:   serial0@ffc02000
Net:   
Warning: ethernet@ff800000 (eth0) using random MAC address - 06:ae:11:53:08:53
eth0: ethernet@ff800000
Hit any key to stop autoboot:  5  4  3  2  1  0 
switch to partitions #0, OK
mmc0 is current device
** No partition table - mmc 0 **
Couldn't find partition mmc 0:1
SF: Detected mt25qu02g with page size 256 Bytes, erase size 64 KiB, total 256 MiB
Select Environment on UBI: OK
Saving Environment to UBI... denali-nand-dt nand@ffb90000: timeout while waiting for irq 0x2000
denali-nand-dt nand@ffb90000: reset not completed.
Could not find a valid device for nand.0
done
OK
UBI partition 'root' already selected
UBI partition 'root' already selected
No size specified → Using max size (196224)
Read 196224 bytes from volume script to 0000000005ff0000
QSPI: Running script from UBIFS
QSPI: Trying to boot script at 0x05FF0000
## Executing script at 05ff0000
crc32+ Trying to boot Linux from device qspi
Device nand0 not found!
UBI partition 'root' already selected
No size specified → Using max size (25182080)
Read 25182080 bytes from volume kernel to 0000000001000000
## Loading kernel from FIT Image at 01000000 …
   Using 'board-4' configuration
   Verifying Hash Integrity … OK
   Trying 'kernel' kernel subimage
     Description:  Linux Kernel
     Type:         Kernel Image
     Compression:  lzma compressed
     Data Start:   0x010000dc
     Data Size:    9521379 Bytes = 9.1 MiB
     Architecture: AArch64
     OS:           Linux
     Load Address: 0x06000000
     Entry Point:  0x06000000
     Hash algo:    crc32
     Hash value:   474b072b
   Verifying Hash Integrity … crc32+ OK
## Loading fdt from FIT Image at 01000000 …
   Using 'board-4' configuration
   Verifying Hash Integrity … OK
   Trying 'fdt-4' fdt subimage
     Description:  socfpga_socdk_combined
     Type:         Flat Device Tree
     Compression:  uncompressed
     Data Start:   0x019253b0
     Data Size:    36985 Bytes = 36.1 KiB
     Architecture: AArch64
     Hash algo:    crc32
     Hash value:   9dd4ce96
   Verifying Hash Integrity … crc32+ OK
   Booting using the fdt blob at 0x19253b0
Working FDT set to 19253b0
## Loading fpga from FIT Image at 01000000 …
   Trying 'fpga-4' fpga subimage
     Description:  FPGA bitstream for GHRD
     Type:         FPGA Image
     Compression:  uncompressed
     Data Start:   0x01cc859c
     Data Size:    3747840 Bytes = 3.6 MiB
     Load Address: 0x0a000000
     Hash algo:    crc32
     Hash value:   27c307b7
   Verifying Hash Integrity … crc32+ OK
   Loading fpga from 0x01cc859c to 0x0a000000
….FPGA reconfiguration OK!
Enable FPGA bridges
   Programming full bitstream... OK
   Uncompressing Kernel Image
   Loading Device Tree to 000000007ead1000, end 000000007eadd078 … OK
Working FDT set to 7ead1000
SF: Detected mt25qu02g with page size 256 Bytes, erase size 64 KiB, total 256 MiB
Enabling QSPI at Linux DTB...
Working FDT set to 7ead1000
libfdt fdt_path_offset() returned FDT_ERR_NOTFOUND
libfdt fdt_path_offset() returned FDT_ERR_NOTFOUND
QSPI clock frequency updated
RSU: Firmware or flash content not supporting RSU
RSU: Firmware or flash content not supporting RSU
RSU: Firmware or flash content not supporting RSU
RSU: Firmware or flash content not supporting RSU

Starting kernel …

Deasserting all peripheral resets
[    0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034]
[    0.000000] Linux version 6.1.68-altera (oe-user@oe-host) (aarch64-poky-linux-gcc (GCC) 13.2.0, GNU ld (GNU Binutils) 2.41.0.20231213) #1 SMP PREEMPT Thu Mar 28 07:56:27 UTC 2024
[    0.000000] Machine model: SoCFPGA Stratix 10 SoCDK

…

[  263.078832] socfpga-dwmac ff804000.ethernet eth2: registered PTP clock
[  263.085838] socfpga-dwmac ff804000.ethernet eth2: configuring for phy/sgmii link mode
[  OK  ] Finished OpenSSH Key Generation.
[  266.826025] socfpga-dwmac ff800000.ethernet eth0: Link is Up - 1Gbps/Full - flow control rx/tx
[  266.834698] IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready
[  266.864773] 8021q: 802.1Q VLAN Support v1.8

Poky (Yocto Project Reference Distro) 4.3.4 stratix10 ttyS0

stratix10 login: root

root@stratix10:~#

Note: First time Linux is booted, the UBIFS rootfs will be initialized, the step taking approximately 3 minutes, as shown in the log below: 

[   12.523260] platform soc:leds: deferred probe pending
 … 3 minute 'gap' here ...
[  205.105071] UBIFS (ubi0:4): free space fixup complete
[  205.234501] UBIFS (ubi0:4): UBIFS: mounted UBI device 0, volume 4, name "rootfs"
[  205.241896] UBIFS (ubi0:4): LEB size: 65408 bytes (63 KiB), min./max. I/O unit sizes: 8 bytes/256 bytes
[  205.251273] UBIFS (ubi0:4): FS size: 167117440 bytes (159 MiB, 2555 LEBs), max 6500 LEBs, journal size 8650240 bytes (8 MiB, 133 LEBs)

On the first boot empty pages are identifies and erased, to ensure all pages are 0xFF and avoid problematic non-0xFF empty page. This is controlled by the "-F" parameter passed when creating the rootfs.ubifs image. The next boots will not have this this step. Refer to http://www.linux-mtd.infradead.org/faq/ubifs.html for more details.

Booting From NAND

This section presents how to boot the Stratix 10 SoC from NAND, including how to build all binaries.

Build instructions are the same as for standard SD or QSPI boot. The U-Boot, ATF and Linux binaries are all the same. The only differences are:
  • GHRD is configured for the NAND HPS Daughtercard, then recompiled
  • The PR persona.rbf files are the ones compiled by the GHRD configured for NAND

Note: As the NAND used on the devkit has a smaller size than the SD card (1GB vs 2GB) the rootfs is smaller, and less functionality is provided. The purpose of this section is just to show Linux booting.

NAND Daughtercard

The NAND/eMMC HPS daughtercard that comes with the S10 SoC DevKit supports both NAND and eMMC.

To configure the card for NAND operation, please set the jumpers as shown below:

Jumper Setting
J2 unpopulated
J9 unpopulated
J10 populated 2-3
J11 populated 1-1

For reference, the NAND/eMMC schematic is available at https://www.intel.com/content/dam/altera-www/global/en_US/support/boards-kits/arria10/soc/hps_io48_nand_dc.pdf.

NAND Flash Layout

MTD Partition UBI Volume Volume Name Type Image/File Flash Offset Size Size in Hex
0 (u-boot) N/A N/A RAW u-boot.itb 0x00000000 2MB 0x00200000
1 (root) 0 env UBI u-boot.env root.ubi 0x00200000
onwards 		256KB 0x40000
1 script UBI u-boot.scr 128KB 0x00020000
2 kernel UBI kernel.itb 64MB 0x04000000
3 dtb UBI kernel.dtb 256KB 0x00040000
4 rootfs UBIFS rootfs.ubifs <957MB <0x3BD70000

Setting up Environment

Create a top folder for this example, as the rest of the commands assume this location: 

sudo rm -rf stratix10_gsrd.nand
mkdir stratix10_gsrd.nand
cd stratix10_gsrd.nand
export TOP_FOLDER=$(pwd)

Download the compiler toolchain, add it to the PATH variable, to be used by the GHRD makefile to build the HPS Debug FSBL: 

cd $TOP_FOLDER
wget https://developer.arm.com/-/media/Files/downloads/gnu/11.2-2022.02/binrel/\
gcc-arm-11.2-2022.02-x86_64-aarch64-none-linux-gnu.tar.xz
tar xf gcc-arm-11.2-2022.02-x86_64-aarch64-none-linux-gnu.tar.xz
rm -f gcc-arm-11.2-2022.02-x86_64-aarch64-none-linux-gnu.tar.xz
export PATH=`pwd`/gcc-arm-11.2-2022.02-x86_64-aarch64-none-linux-gnu/bin:$PATH
export ARCH=arm64
export CROSS_COMPILE=aarch64-none-linux-gnu-

Enable Quartus tools to be called from command line: 

export QUARTUS_ROOTDIR=~/intelFPGA_pro/24.1/quartus/
export PATH=$QUARTUS_ROOTDIR/bin:$QUARTUS_ROOTDIR/linux64:$QUARTUS_ROOTDIR/../qsys/bin:$PATH

Building the Hardware Design

Build the GHRD targeting the NAND HPS daughtercard, by passing the correct parameter to the make utility: 

cd $TOP_FOLDER
rm -rf ghrd-socfpga s10_soc_devkit_ghrd
git clone -b QPDS24.1_REL_GSRD_PR https://github.com/altera-opensource/ghrd-socfpga
mv ghrd-socfpga/s10_soc_devkit_ghrd .
rm -rf ghrd-socfpga
cd s10_soc_devkit_ghrd
export DAUGHTER_CARD=devkit_dc_nand
make scrub_clean_all
make generate_from_tcl
make all
unset DAUGHTER_CARD
cd ..

The following files are created in $TOP_FOLDER/s10_soc_devkit_ghrd/output_files:
  • ghrd_1sx280lu2f50e2vg.sof - FPGA SOF file, without HPS FSBL
  • ghrd_1sx280lu2f50e2vg_hps_debug.sof - FPGA SOF, with HPS Debug FSBL
  • ghrd_1sx280lu2f50e2vg.pr_partition_0.rbf - PR bitsream for the baseline persona
  • alternate_persona.pr_partition_0.rbf - PR bitstream for the alternate persona

Building Core RBF

Create the Core RBF file to be used in the rootfs created by Yocto by using the HPS Debug SOF built by the GHRD makefile: 

cd $TOP_FOLDER
quartus_pfg -c s10_soc_devkit_ghrd/output_files/ghrd_1sx280lu2f50e2vg_hps_debug.sof \
  ghrd_1sx280lu2f50e2vg.jic \
  -o device=MT25QU02G \
  -o flash_loader=1SX280LU2 \
  -o mode=ASX4 \
  -o hps=1
rm ghrd_1sx280lu2f50e2vg.hps.jic

The following files will be created:
  • $TOP_FOLDER/ghrd_1sx280lu2f50e2vg.core.rbf - HPS First configuration bitstream, phase 2: FPGA fabric

Note we are also creating an HPS JIC file, but we are discarding it, as it has the HPS Debug FSBL, while the final image needs to have the U-Boot SPL created by the Yocto recipes.

Setting Up Yocto Build System

1. First, make sure you have Yocto system requirements met: https://docs.yoctoproject.org/3.4.1/ref-manual/system-requirements.html#supported-linux-distributions. The command to install the required packages on Ubuntu 20.04 is: 

sudo apt-get update
sudo apt-get upgrade
sudo apt-get install openssh-server mc libgmp3-dev libmpc-dev gawk wget git diffstat unzip texinfo gcc \
build-essential chrpath socat cpio python3 python3-pip python3-pexpect xz-utils debianutils iputils-ping \
python3-git python3-jinja2 libegl1-mesa libsdl1.2-dev pylint3 xterm python3-subunit mesa-common-dev zstd \
liblz4-tool git fakeroot build-essential ncurses-dev xz-utils libssl-dev bc flex libelf-dev bison xinetd \
tftpd tftp nfs-kernel-server libncurses5 libc6-i386 libstdc++6:i386 libgcc++1:i386 lib32z1 \
device-tree-compiler curl mtd-utils u-boot-tools net-tools swig -y

On Ubuntu 20.04 you will also need to point the /bin/sh to /bin/bash, as the default is a link to /bin/dash: 

 sudo ln -sf /bin/bash /bin/sh

Note: You can also use a Docker container to build the Yocto recipes, refer to https://rocketboards.org/foswiki/Documentation/DockerYoctoBuild for details. When using a Docker container, it does not matter what Linux distribution or packages you have installed on your host, as all dependencies are provided by the Docker container.

2. Clone the Yocto script and prepare the build: 
cd $TOP_FOLDER
rm -rf gsrd_socfpga
git clone -b nanbield https://github.com/altera-opensource/gsrd_socfpga
cd gsrd_socfpga
. stratix10-gsrd-build.sh
build_setup

Note: Run the following commands to set up again the yocto build environments, if you closed the current window (for example when rebooting the Linux host) and want to resume the next steps: 

cd $TOP_FOLDER/gsrd_socfpga
. ./poky/oe-init-build-env stratix10-gsrd-rootfs/

Customize Yocto Build

1. Copy the rebuilt files to $WORKSPACE/meta-intel-fpga-refdes/recipes-bsp/ghrd/files using the following names, as expected by the yocto recipes:
  • stratix10_gsrd_ghrd.core.rbf: not applicable, as we have not rebuilt the standard GSRD version supporting SD card in this case
  • stratix10_pr_persona0.rbf
  • stratix10_pr_persona1.rbf
  • stratix10_nand_ghrd.core.rbf
This can be accomplished using the following instructions: 
GHRD_LOC=$WORKSPACE/meta-intel-fpga-refdes/recipes-bsp/ghrd/files
CORE_RBF=$GHRD_LOC/stratix10_nand_ghrd.core.rbf
PER0_RBF=$GHRD_LOC/stratix10_pr_persona0.rbf 
PER1_RBF=$GHRD_LOC/stratix10_pr_persona1.rbf
cp $TOP_FOLDER/ghrd_1sx280lu2f50e2vg.core.rbf $CORE_RBF
cp $TOP_FOLDER/s10_soc_devkit_ghrd/output_files/ghrd_1sx280lu2f50e2vg.pr_partition_0.rbf $PER0_RBF
cp $TOP_FOLDER/s10_soc_devkit_ghrd/output_files/alternate_persona.pr_partition_0.rbf $PER1_RBF

2. Update the Yocto recipe at $WORKSPACE/meta-intel-fpga-refdes/recipes-bsp/ghrd/hw-ref-design.bb to change the SRC_URI:stratix10 from the orginal value: 
SRC_URI:stratix10 ?= "\
      ${GHRD_REPO}/stratix10_gsrd_${ARM64_GHRD_CORE_RBF};name=stratix10_gsrd_core \
      ${GHRD_REPO}/stratix10_nand_${ARM64_GHRD_CORE_RBF};name=stratix10_nand_core \
      ${GHRD_REPO}/stratix10_pr_persona0.rbf;name=stratix10_pr_persona0 \
      ${GHRD_REPO}/stratix10_pr_persona1.rbf;name=stratix10_pr_persona1 \
      "
to be: 
SRC_URI:stratix10 ?= "\
      ${GHRD_REPO}/stratix10_gsrd_${ARM64_GHRD_CORE_RBF};name=stratix10_gsrd_core \      
      file://stratix10_nand_ghrd.core.rbf \
      file://stratix10_pr_persona0.rbf \
      file://stratix10_pr_persona1.rbf \
      "
using the following commands from the console: 
OLD_CORE_URI="\${GHRD_REPO}\/stratix10_nand_\${ARM64_GHRD_CORE_RBF};name=stratix10_nand_core"
NEW_CORE_URI="file:\/\/stratix10_nand_ghrd.core.rbf"
OLD_PER0_URI="\${GHRD_REPO}\/stratix10_pr_persona0.rbf;name=stratix10_pr_persona0"
NEW_PER0_URI="file:\/\/stratix10_pr_persona0.rbf"
OLD_PER1_URI="\${GHRD_REPO}\/stratix10_pr_persona1.rbf;name=stratix10_pr_persona1"
NEW_PER1_URI="file:\/\/stratix10_pr_persona1.rbf"
RECIPE=$WORKSPACE/meta-intel-fpga-refdes/recipes-bsp/ghrd/hw-ref-design.bb
sed -i "s/$OLD_CORE_URI/$NEW_CORE_URI/g" $RECIPE
sed -i "s/$OLD_PER0_URI/$NEW_PER0_URI/g" $RECIPE
sed -i "s/$OLD_PER1_URI/$NEW_PER1_URI/g" $RECIPE
Note we have left the NAND file alone, that will be downloaded from rocketboards.

3. Update the same Yocto recipe to change the SHA checksums for the new files: 
SRC_URI[stratix10_gsrd_core.sha256sum] = "ea26a77ebc1b3141193de6dd32e22f332785e05c956de85118c3790392141d3c"
SRC_URI[stratix10_nand_core.sha256sum] = "d782c05085f8f13cb792b687fd002773e0897e4d7ecf5451994b1823d62cdc92"
SRC_URI[stratix10_pr_persona0.sha256sum] = "60af20604f8756b251d3bff23ceaf8c4edec6d37cf4558ed763e1e311ab4c81e"
SRC_URI[stratix10_pr_persona1.sha256sum] = "c555e432574431ec0d2596fe7dc3f4ace86899add91599023d26127a9d78293b"
to the new values using the following commands: 
CORE_SHA=$(sha256sum $CORE_RBF | cut -f1 -d" ")
PER0_SHA=$(sha256sum $PER0_RBF | cut -f1 -d" ")
PER1_SHA=$(sha256sum $PER1_RBF | cut -f1 -d" ")
OLD_CORE_SHA="SRC_URI\[stratix10_nand_core\.sha256sum\] = .*"
NEW_CORE_SHA="SRC_URI[stratix10_nand_core.sha256sum] =  \"$CORE_SHA\""
OLD_PER0_SHA="SRC_URI\[stratix10_pr_persona0\.sha256sum\] = .*"
NEW_PER0_SHA="SRC_URI[stratix10_pr_persona0.sha256sum] =  \"$PER0_SHA\""
OLD_PER1_SHA="SRC_URI\[stratix10_pr_persona1\.sha256sum\] = .*"
NEW_PER1_SHA="SRC_URI[stratix10_pr_persona1.sha256sum] =  \"$PER1_SHA\""
sed -i "s/$OLD_CORE_SHA/$NEW_CORE_SHA/g" $RECIPE
sed -i "s/$OLD_PER0_SHA/$NEW_PER0_SHA/g" $RECIPE
sed -i "s/$OLD_PER1_SHA/$NEW_PER1_SHA/g" $RECIPE

4. Optionally change the following files in $WORKSPACE/meta-intel-fpga-refdes/recipes-bsp/u-boot/files/:

5. Optionally change the following file in $WORKSPACE/meta-intel-fpga-refdes/recipes-kernel/linux/linux-socfpga-lts:
  • fit_kernel_stratix10.its - its file for creating the kernel.itb image, containing by default:
    • Kernel
    • Device trees for SD and NAND board configurations
    • Core RBF files for SD and NAND board configurations
    • Board configurations for SD and NAND cases

Build Yocto

Build Yocto: 
bitbake_image

Gather files: 
package

Once the build is completed successfully, you will see the following two folders are created:

The two most relevant files created in the $TOP_FOLDER/gsrd_socfpga/stratix10-gsrd-images folder are:

File Description
gsrd-console-image-stratix10_nand.ubifs UBI root partition image
u-boot-stratix10-socdk-gsrd-atf/u-boot.itb U-Boot FIT image
u-boot-stratix10-socdk-gsrd-atf/u-boot-spl-dtb.hex U-Boot SPL Hex file

Building QSPI Flash Image

The QSPI image will contain the FPGA configuration data and the HPS FSBL and it can be built using the following command: 

cd $TOP_FOLDER
quartus_pfg -c s10_soc_devkit_ghrd/output_files/ghrd_1sx280lu2f50e2vg.sof \
  ghrd_1sx280lu2f50e2vg.jic \
  -o device=MT25QU02G \
  -o flash_loader=1SX280LU2 \
  -o hps_path=gsrd_socfpga/stratix10-gsrd-images/u-boot-stratix10-socdk-gsrd-atf/u-boot-spl-dtb.hex \
  -o mode=ASX4 \
  -o hps=1

The following files will be created:
  • $TOP_FOLDER/ghrd_1sx280lu2f50e2vg.hps.jic - Flash image for HPS First configuration bitstream, phase 1: HPS and DDR
  • $TOP_FOLDER/ghrd_1sx280lu2f50e2vg.core.rbf - HPS First configuration bitstream, phase 2: FPGA fabric. We already have the same file on the SD card.

Building NAND Binaries

1. Gather the files into a single folder, using symlinks: 

cd $TOP_FOLDER
rm -rf nand-bin && mkdir nand-bin && cd nand-bin
ln -s $TOP_FOLDER/gsrd_socfpga/stratix10-gsrd-images/u-boot-stratix10-socdk-gsrd-atf/boot.scr.uimg .
ln -s $TOP_FOLDER/gsrd_socfpga/stratix10-gsrd-images/kernel.itb .
ln -s $TOP_FOLDER/gsrd_socfpga/stratix10-gsrd-images/gsrd-console-image-stratix10_nand.ubifs rootfs.ubifs
ln -s $TOP_FOLDER/gsrd_socfpga/stratix10-gsrd-images/socfpga_stratix10_socdk_nand.dtb .

2. Install mtd-tools if not already installed. On Ubuntu the command is: 

sudo apt-get install mtd-tools

3. Create UBI configuration file for the root partition; 
cat <<EOT >ubinize.cfg 
[env]
mode=ubi
vol_id=0
vol_name=env
vol_size=256KiB
vol_type=dynamic

[script]
mode=ubi
image=boot.scr.uimg
vol_id=1
vol_name=script
vol_size=128KiB
vol_type=dynamic

[kernel]
mode=ubi
image=kernel.itb     
vol_id=2
vol_name=kernel
vol_size=64MiB
vol_type=dynamic

[dtb]
mode=ubi
image=socfpga_stratix10_socdk_nand.dtb
vol_id=3
vol_name=dtb
vol_size=256KiB
vol_type=dynamic

[rootfs]
mode=ubi
image=rootfs.ubifs
vol_id=4
vol_name=rootfs
vol_type=dynamic
vol_size=400MiB
vol_flag=autoresizeENDCOLOR%
EOT

4. Create the root.ubi file: 
ubinize -o root.ubi -p 128KiB -m 2048 -s 2048 ubinize.cfg

This is what the above parameters mean:
  • -p: physical eraseblock size of the flash
  • -m: minimum input/output unit size of the flash
  • -s: sub-pages and sub-page size, ubinize will take into account and put the VID header to same NAND page as the EC header

The following file is created:
  • $TOP_FOLDER/nand-bin/root.ubi

Write NAND Binaries

Write Binaries to NAND

1. Copy files to your TFTP server folder: 

cp -f $TOP_FOLDER/gsrd_socfpga/stratix10-gsrd-images/u-boot-stratix10-socdk-gsrd-atf/u-boot.itb<your-tftp-server-folder>
cp -f $TOP_FOLDER/nand-bin/root.ubi <your-tftp-server-folder>

2. Run U-Boot with the debugger, similar to how it is described at https://rocketboards.org/foswiki/Documentation/BuildingBootloader#Stratix_10_SOC_45_Run_U_45Boot_from_Debugger just change the script to use the binaries directly from $TOP_FOLDER/gsrd_socfpga/stratix10-gsrd-images/u-boot-stratix10-socdk-gsrd-atf/.

3. Stop at U-Boot prompt, and run the following instructions to download and write NAND binaries to flash: 

setenv autoload no
dhcp
setenv serverip <your-tftp-server-ip>

tftp $loadaddr u-boot.itb
nand erase.part u-boot
nand write $loadaddr u-boot $filesize

tftp $loadaddr root.ubi
nand erase.part clean root
nand write.trimffs $loadaddr root $filesize

Write QSPI Image

1. Power off board

2. Set MSEL to JTAG

3. Power on board

4. Write jic image to QSPI: 

cd $TOP_FOLDER
quartus_pgm -c 1 -m jtag -o "pvi;ghrd_1sx280lu2f50e2vg.hps.jic"

Booting Linux

1. Power off the board. Make sure MSEL is set to QSPI.

2. Power on the board.

3. Linux will boot, use 'root' as username, with no password: 

U-Boot SPL 2023.10 (Mar 21 2024 - 07:41:59 +0000)
Reset state: Cold
MPU         1000000 kHz
L3 main     400000 kHz
Main VCO    2000000 kHz
Per VCO     2000000 kHz
EOSC1       25000 kHz
HPS MMC     100 kHz
UART        100000 kHz
DDR: 4096 MiB
SDRAM-ECC: Initialized success with 1176 ms
QSPI: Reference clock at 400000 kHz
WDT:   Started watchdog@ffd00200 with servicing every 1000ms (10s timeout)
Trying to boot from MMC1
spl: mmc init failed with error: -110
Trying to boot from SPI
Trying to boot from NAND
## Checking hash(es) for config board-1 … OK
## Checking hash(es) for Image atf … crc32+ OK
## Checking hash(es) for Image uboot … crc32+ OK
## Checking hash(es) for Image fdt-1 … crc32+ OK
NOTICE:  BL31: v2.10.0	(release):v2.3-6547-gafecefc0f
NOTICE:  BL31: Built : 08:52:03, Mar 21 2024

U-Boot 2023.10 (Mar 21 2024 - 07:41:59 +0000)socfpga_stratix10

CPU:   Intel FPGA SoCFPGA Platform (ARMv8 64bit Cortex-A53)
Model: SoCFPGA Stratix 10 SoCDK
DRAM:  2 GiB (effective 4 GiB)
Core:  24 devices, 20 uclasses, devicetree: separate
WDT:   Started watchdog@ffd00200 with servicing every 1000ms (10s timeout)
NAND:  1024 MiB
MMC:   
Loading Environment from FAT... ** Bad device specification mmc 0 **
Loading Environment from UBI... SF: Detected mt25qu02g with page size 256 Bytes, erase size 64 KiB, total 256 MiB
mtd: partition "Root Filesystem - JFFS2" extends beyond the end of device "nor0" -- size truncated to 0xcb50000
Read 8192 bytes from volume env to 000000007fae2500
*** Warning - bad CRC, using default environment

In:    serial0@ffc02000
Out:   serial0@ffc02000
Err:   serial0@ffc02000
Net:   
Warning: ethernet@ff804000 (eth2) using random MAC address - 42:08:20:8a:a8:20
eth2: ethernet@ff804000
Hit any key to stop autoboot:  5  4  3  2  1  0 
No MMC device available
SF: Detected mt25qu02g with page size 256 Bytes, erase size 64 KiB, total 256 MiB
Select Environment on UBI: OK
Saving Environment to UBI... ubi0 error: ubi_read_volume_table: the layout volume was not found
ubi0 error: ubi_attach_mtd_dev: failed to attach mtd3, error -22
UBI error: cannot attach mtd3
UBI error: cannot initialize UBI, error -22
UBI init error 22
Please check, if the correct MTD partition is used (size big enough?)

** Cannot find mtd partition "root"
Failed (1)
QSPI: Trying to boot script at 0x05FF0000
## Executing script at 05ff0000
Wrong image format for "source" command
QSPI: SCRIPT FAILED: continuing...
Select Environment on UBI: OK
Saving Environment to UBI... done
OK
UBI partition 'root' already selected
No size specified → Using max size (253952)
Read 253952 bytes from volume script to 0000000005ff0000
NAND: Trying to boot script at 0x05FF0000
## Executing script at 05ff0000
crc32+ Trying to boot Linux from device nand
Select Environment on UBI: OK
Saving Environment to UBI... UBI partition 'root' already selected
done
OK

device nor0 , # parts = 2
 #: name		size		offset		mask_flags
 0: u-boot              0x04200000	0x00000000	0
 1: qspi_root           0x0be00000	0x04200000	0

device nand0 , # parts = 2
 #: name		size		offset		mask_flags
 0: u-boot              0x00200000	0x00000000	0
 1: root                0x3fe00000	0x00200000	0

active partition: nor0,0 - (u-boot) 0x04200000 @ 0x00000000

defaults:
mtdids  : nand0=ffb90000.nand.0
mtdparts: mtdparts=ffb90000.nand.0:2m(u-boot),-(root)
UBI partition 'root' already selected
No size specified → Using max size (67170304)
Read 67170304 bytes from volume kernel to 0000000001000000
## Loading kernel from FIT Image at 01000000 …
   Using 'board-1' configuration
   Verifying Hash Integrity … OK
   Trying 'kernel' kernel subimage
     Description:  Linux Kernel
     Type:         Kernel Image
     Compression:  lzma compressed
     Data Start:   0x010000dc
     Data Size:    9521379 Bytes = 9.1 MiB
     Architecture: AArch64
     OS:           Linux
     Load Address: 0x06000000
     Entry Point:  0x06000000
     Hash algo:    crc32
     Hash value:   474b072b
   Verifying Hash Integrity … crc32+ OK
## Loading fdt from FIT Image at 01000000 …
   Using 'board-1' configuration
   Verifying Hash Integrity … OK
   Trying 'fdt-1' fdt subimage
     Description:  socfpga_socdk_nand
     Type:         Flat Device Tree
     Compression:  uncompressed
     Data Start:   0x0191c508
     Data Size:    36342 Bytes = 35.5 KiB
     Architecture: AArch64
     Hash algo:    crc32
     Hash value:   2edf432a
   Verifying Hash Integrity … crc32+ OK
   Booting using the fdt blob at 0x191c508
Working FDT set to 191c508
## Loading fpga from FIT Image at 01000000 …
   Trying 'fpga-1' fpga subimage
     Description:  FPGA bitstream for NAND
     Type:         FPGA Image
     Compression:  uncompressed
     Data Start:   0x0192e4dc
     Data Size:    3776512 Bytes = 3.6 MiB
     Load Address: 0x0a000000
     Hash algo:    crc32
     Hash value:   636b3b1d
   Verifying Hash Integrity … crc32+ OK
   Loading fpga from 0x0192e4dc to 0x0a000000
….FPGA reconfiguration OK!
Enable FPGA bridges
   Programming full bitstream... OK
   Uncompressing Kernel Image
   Loading Device Tree to 000000007ead4000, end 000000007eadfdf5 … OK
Working FDT set to 7ead4000
SF: Detected mt25qu02g with page size 256 Bytes, erase size 64 KiB, total 256 MiB
Enabling QSPI at Linux DTB...
Working FDT set to 7ead4000
libfdt fdt_path_offset() returned FDT_ERR_NOTFOUND
libfdt fdt_path_offset() returned FDT_ERR_NOTFOUND
QSPI clock frequency updated
RSU: Firmware or flash content not supporting RSU
RSU: Firmware or flash content not supporting RSU
RSU: Firmware or flash content not supporting RSU
RSU: Firmware or flash content not supporting RSU

Starting kernel …

Deasserting all peripheral resets
[    0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034]
[    0.000000] Linux version 6.1.68-altera (oe-user@oe-host) (aarch64-poky-linux-gcc (GCC) 13.2.0, GNU ld (GNU Binutils) 2.41.0.20231213) #1 SMP PREEMPT Thu Mar 28 07:56:27 UTC 2024
[    0.000000] Machine model: SoCFPGA Stratix 10 SoCDK

…

[    9.442993] i2c_designware ffc02a00.i2c: controller timed out
[   10.467000] i2c_designware ffc02a00.i2c: controller timed out
[   12.900585] socfpga-dwmac ff804000.ethernet eth2: Link is Up - 1Gbps/Full - flow control rx/tx
[   12.909268] IPv6: ADDRCONF(NETDEV_CHANGE): eth2: link becomes ready
[   12.932331] 8021q: 802.1Q VLAN Support v1.8

Poky (Yocto Project Reference Distro) 4.3.4 stratix10 ttyS0

stratix10 login: root

root@stratix10:~#

Partial Reconfiguration

Partial reconfiguration (PR) allows you to reconfigure a portion of the FPGA dynamically, while the rest of the FPGA design continues to function.

The Stratix 10 SoC GSRD supports PR (Partial Reconfiguration) in all scenarios above:
  • Booting from SD card
  • Booting from QSPI
  • Booting from NAND

Reference Information

Refer to the following fore more details about Partial Reconfiguration

Hardware Design

The GHRD contains the following components which enable PR:
  • A PR region was created in the FPGA fabric, with the following associated IP
    • PR Freeze Controller - to help control the PR
    • Avalon-MM PR Freeze Bridge - to help isolate the IP in the PR region during the PR process
  • The base revision of the project has the following in the PR region:
    • SysID located at 0xF900_0800: with id=0xfacecafe
    • OCRAM located at 0xF900_0900
  • An alternate revision of the project contains the following in the PR region:
    • SysID located at 0xF900_0900: with id=0xcafeface
    • OCRAM located at 0xF900_0800

The following diagram presents an overview of the PR region and associated IP and how it is connected to HPS:

pr-hwdesign.png

Throughout this page, the content of the PR region for the base revision is called "persona0" while the content of the PR region for the other revision is called "persona1". The diagram below illustrates the differences between the two personas:

pr-personas.png

PR Files

The files on the Linux rootfs used for running the PR scenarios are shown below:

File Description
/sbin/dtbt Tool used for managing the overlays. Available at https://github.com/altera-opensource/dtbt
/boot/devicetree/stratix10_pr_fpga_static_region.dtbo overlay for the static region, needs to be applied before persona overlays
/boot/devicetree/stratix10_pr_persona0.dtbo overlay for persona0
/boot/devicetree/stratix10_pr_persona1.dtbo overlay for persona1
/lib/firmware/persona0.rbf bitstream used by persona0 overlay
/lib/firmware/persona1.rbf bitstream used by persona1 overlay

The DTS files for the overlays are available at https://github.com/altera-opensource/meta-intel-fpga-refdes/blob/langdale/recipes-bsp/device-tree/files/:
  • stratix10_pr_fpga_static_region.dts
  • stratix10_pr_persona0.dts
  • stratix10_pr_persona1.dts

Running PR Scenarios

1. Boot Linux

2. Add the overlay for the static region: 

root@stratix10:~# dtbt -a stratix10_pr_fpga_static_region.dtbo -p /boot/devicetree
Set dtbo search path to /boot
Applying dtbo: fpga_static_region.dtbo
[  141.686353] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /soc/base_fpga_region/ranges
[  141.698256] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /soc/base_fpga_region/external-fpga-config
[  141.709907] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /soc/base_fpga_region/clocks
[  141.720335] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /soc/base_fpga_region/clock-names
[  141.731276] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/clk_0
[  141.740852] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/freeze_controller_0
[  141.756396] of-fpga-region soc:base_fpga_region:fpga_pr_region0: FPGA Region probed
[  141.780483] altera_freeze_br f9000450.freeze_controller: fpga bridge [freeze] registered

3. Add the overlay for persona0: 

root@stratix10:~# dtbt -a stratix10_pr_persona0.dtbo -p /boot/devicetree 
Set dtbo search path to /boot
Applying dtbo: persona0.dtbo
[  190.741610] fpga_manager fpga0: writing persona0.rbf to Stratix10 SOC FPGA Manager
[  191.251227] svc_normal_to_secure_thread: STATUS_ERROR
[  191.251871] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/pr_region_0_pr_clk_100
[  191.266963] svc_normal_to_secure_thread: STATUS_ERROR
[  191.267349] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/pr_region_0_pr_sysid_qsys_0
[  191.282704] svc_normal_to_secure_thread: STATUS_ERROR

4. Locate the sysid and display the associated id: 

root@stratix10:~# find / -name sysid
/sys/devices/platform/soc/soc:base_fpga_region/soc:base_fpga_region:fpga_pr_region0/f9000800.sysid/sysid
root@stratix10:~# cat /sys/devices/platform/soc/soc:base_fpga_region/soc:base_fpga_region:fpga_pr_region0/f9000800.sysid/sysid/id | xargs printf "0x%08x\n"
0xcafeface

5. List the applied overlays: 

root@stratix10:~# dtbt -l
2 persona0.dtbo applied /sys/kernel/config/device-tree/overlays/2-persona0.dtbo
1 fpga_static_region.dtbo applied /sys/kernel/config/device-tree/overlays/1-fpga_static_region.dtbo

6. Remove persona0 overlay: 

root@stratix10:~# dtbt -r stratix10_pr_persona0.dtbo -p /boot/devicetree
Set dtbo search path to /boot
Removing dtbo: 2-persona0.dtbo

7. Add the persona1 overlay: 

root@stratix10:~# dtbt -a stratix10_pr_persona1.dtbo -p /boot/devicetree
Set dtbo search path to /boot
Applying dtbo: persona1.dtbo
[  343.885073] fpga_manager fpga0: writing persona1.rbf to Stratix10 SOC FPGA Manager
[  344.385019] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/pr_region_0_pr_clk_100
[  344.396098] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/pr_region_0_pr_sysid_qsys_0

8. Locate the sysid and display the associated id: 

root@stratix10:~# find / -name sysid
/sys/devices/platform/soc/soc:base_fpga_region/soc:base_fpga_region:fpga_pr_region0/f9000900.sysid/sysid
root@stratix10:~# cat /sys/devices/platform/soc/soc:base_fpga_region/soc:base_fpga_region:fpga_pr_region0/f9000900.sysid/sysid/id | xargs printf "0x%08x\n"
0xfacecafe

9. Remove persona1: 

root@stratix10:~# dtbt -r stratix10_pr_persona1.dtbo -p /boot/devicetree
Set dtbo search path to /boot
Removing dtbo: 2-persona1.dtbo

10. List the applied overlays: 

root@stratix10:~# dtbt -l
1 fpga_static_region.dtbo applied /sys/kernel/config/device-tree/overlays/1-fpga_static_region.dtbo

Disabling Unused Flash Devices in U-Boot for Faster Booting

This release of the GSRD uses the same U-Boot binaries to boot from all supported flash devices: SD, QSPI and NAND.

U-Boot will try to initialize all the flash devices, adding to the boot time. You can disable the unused flash devices by doing the following:
  • Change U-Boot defconfig to remove support for the flash
  • Change U-Boot device tree to disable the flash, and not try to boot from it.

The following shows for example how to disable NAND support, by adding another Yocto layer containing a new U-Boot patch:

1. Set up Yocto build using the standard instructions: 

cd $TOP_FOLDER
rm -rf gsrd_socfpga
git clone -b nanbield https://github.com/altera-opensource/gsrd_socfpga
cd gsrd_socfpga
. stratix10-gsrd-build.sh
build_setup

2. Customize Yocto build as necessary to use the recompiled GHRD files for example, using the standard instructions.

3. Use devtool to modify U-Boot to disable NAND support: 

cd $TOP_FOLDER/gsrd_socfpga/stratix10-gsrd-rootfs/
devtool modify virtual/bootloader
cd workspace/sources/u-boot-socfpga
sed -i 's/u-boot,spl-boot-order.*/u-boot\,spl-boot-order = \&mmc;/g' arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi
sed -i '/&nand {/!b;n;c\\tstatus = "disabled";' arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi
sed -i '/NAND/d' configs/socfpga_stratix10_defconfig
git commit -a -m "remove nand support"

4. Create new layer and add the U-Boot patch to it: 

bitbake-layers create-layer $TOP_FOLDER/gsrd_socfpga/meta-modified-project
devtool update-recipe -a $TOP_FOLDER/gsrd_socfpga/meta-modified-project u-boot-socfpga
cd $TOP_FOLDER/gsrd_socfpga/stratix10-gsrd-rootfs/
bitbake-layers add-layer $TOP_FOLDER/gsrd_socfpga/meta-modified-project

5. Remove the temporary layer and workspace created by devtool: 

bitbake-layers remove-layer $TOP_FOLDER/gsrd_socfpga/stratix10-gsrd-rootfs/workspace
rm -rf $TOP_FOLDER/gsrd_socfpga/stratix10-gsrd-rootfs/workspace

6. Buid the Yocto recipes as usual: 

bitbake_image
package

7. Build the rest of the files, as usual.

For reference, the U-Boot patch created by the above instructions looks like this:

From 21c886960e5aac5d74f00b681712ab46e4f77ece Mon Sep 17 00:00:00 2001
From: Radu Bacrau <radu.bacrau@intel.com>
Date: Wed, 9 Mar 2022 09:42:38 -0600
Subject: [PATCH] remove nand support

---
arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi | 4 ++--
configs/socfpga_stratix10_defconfig | 9 ---------
2 files changed, 2 insertions(+), 11 deletions(-)

diff --git a/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi
index 24d47fcd12..16e2104859 100755
--- a/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi
@@ -10,7 +10,7 @@
/{
chosen {
stdout-path = "serial0:115200n8";
- u-boot,spl-boot-order = &mmc,&flash0,&nand;
+ u-boot,spl-boot-order = &mmc;
};

aliases {
@@ -32,7 +32,7 @@
};

&nand {
- status = "okay";
+ status = "disabled";
nand-bus-width = <16>;
u-boot,dm-pre-reloc;
};
diff --git a/configs/socfpga_stratix10_defconfig b/configs/socfpga_stratix10_defconfig
index a63cfeaa44..cd5fbb26f6 100644
--- a/configs/socfpga_stratix10_defconfig
+++ b/configs/socfpga_stratix10_defconfig
@@ -20,7 +20,6 @@ CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x02000000
# CONFIG_USE_SPL_FIT_GENERATOR is not set
-CONFIG_NAND_BOOT=y
CONFIG_QSPI_BOOT=y
CONFIG_BOOTDELAY=5
CONFIG_USE_BOOTARGS=y
@@ -28,7 +27,6 @@ CONFIG_BOOTARGS="earlycon panic=-1"
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_CRC32_SUPPORT=y
CONFIG_SPL_MTD_SUPPORT=y
-CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SPL_ATF=y
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
@@ -40,8 +38,6 @@ CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_MTD=y
-CONFIG_CMD_NAND_TRIMFFS=y
-CONFIG_CMD_NAND_LOCK_UNLOCK=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
CONFIG_CMD_CACHE=y
@@ -73,11 +69,6 @@ CONFIG_MISC=y
CONFIG_MMC_DW=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
-CONFIG_NAND_DENALI_DT=y
-CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
-CONFIG_SYS_NAND_U_BOOT_OFFS=0x0
-CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND=0x100000
-CONFIG_SPL_NAND_FRAMEWORK=y
CONFIG_SF_DEFAULT_MODE=0x2003
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y

Build and package kernel/uboot only.

Note: Run the following commands to set up again the yocto build environments, if you closed the current window (for example when rebooting the Linux host) and want to resume the next steps: 

cd $TOP_FOLDER/gsrd_socfpga
. ./poky/oe-init-build-env stratix10-gsrd-rootfs/

Set up Yocto build: 

cd $TOP_FOLDER
cd gsrd_socfpga
. stratix10-gsrd-build.sh

Linux kernel

if some little modifications for testing/debugging in the kernel are needed then they can be done by executing commands separately.

Kernel configurations: 
 bitbake virtual/kernel -c menuconfig

kernel sourcecode modifications:

A terminal configured and set on Yocto's kernel source code will appear where you can execute commands/ text editors to modify it. 
 bitbake virtual/kernel -c devshell

Note: All changes made to the code and configurations will be erased if clean is called. If you want some more persistent changes then do the following changes:

Configurations:

Create defconfig and copy to Yocto's kernel folder: 

 
bitbake virtual/kernel    -c savedefconfig
cp $TOP_FOLDER//gsrd_socfpga/stratix10-gsrd-rootfs/tmp/work/stratix10-poky-linux/linux-socfpga-lts/*/linux-stratix10-standard-build/defconfig $TOP_FOLDER/gsrd_socfpga/meta-intel-fpga-refdes/recipes-kernel/linux/linux-socfpga-lts/defconfig

Modify 
  $TOP_FOLDER/gsrd_socfpga/meta-intel-fpga-refdes/recipes-kernel/linux/linux-socfpga-lt
s_5.10.bbappend

Search the following lines: 
 # Append GSRD specific kernel config fragments
  SRC_URI += "file://ubifs.scc"
  SRC_URI:append:agilex += "file://sgmii.scc"
  SRC_URI:append:stratix10 += "file://sgmii.scc"
  SRC_URI:append:arria10 += "file://tse.scc"
  SRC_URI:append:cyclone5 += "file://tse.scc"
to be 

 # Append GSRD specific kernel config fragments
  SRC_URI += "file://ubifs.scc"
  SRC_URI:append:agilex += "file://sgmii.scc"
  SRC_URI:append:stratix10 += "file://defconfig"
  SRC_URI:append:arria10 += "file://tse.scc"
  SRC_URI:append:cyclone5 += "file://tse.scc"

Linux source code:

Note: This can also be applied for defconfigs.

First, you should have a .patch where your changes are specified. You can also take one from your changes made directly into yocto by executing this: 

 
bitbake virtual/kernel -c devshell
git diff > mychanges.patch
mv mychanges.patch $TOP_FOLDER/gsrd_socfpga/meta-intel-fpga-refdes/recipes-kernel/linux/linux-socfpga-lts/

Then Modify 
  $TOP_FOLDER/gsrd_socfpga/meta-intel-fpga-refdes/recipes-kernel/linux/linux-socfpga-lt
s_5.10.bbappend

Search the following lines: 
SRC_URI:append:stratix10 += "\
                         file://0001-socfpga_stratix10_socdk-include-combined-ghrd-design.patch \
                         file://fit_kernel_stratix10.its \
                         file://stratix10_pr_fpga_static_region.dtb \
                         file://stratix10_pr_persona0.dtb \
                         file://stratix10_pr_persona1.dtb \
to be 

SRC_URI:append:stratix10 += "\
                         file://0001-socfpga_stratix10_socdk-include-combined-ghrd-design.patch \
                         file://mychanges.patch \
                         file://fit_kernel_stratix10.its \
                         file://stratix10_pr_fpga_static_region.dtb \
                         file://stratix10_pr_persona0.dtb \
                         file://stratix10_pr_persona1.dtb \

Build

Start building 
 bitbake virtual/kernel

Package

Once we have our modified and built kernel we have to package it. 
 package

U-boot

if some little modifications for testing/debugging in the U-Boot are needed then they can be done by executing commands separately.

U-boot sourcecode modifications:

A terminal configured and set on Yocto's U-boot source code will appear where you can execute commands/ text editors to modify it. 
 bitbake  u-boot-socfpga  -c devshell

Note: All changes made to the code will be erased if clean is called. If you want some more persistent changes then do the following changes(also this is the only viable way to modify configurations):

U-boot configurations:

First we have to make our own configurations 

   
   bitbake u-boot-socfpga -c devshell
   cp ../build/socfpga_stratix10_defconfig/.config .config
   CROSS_COMPILE=aarch64-poky-linux- make menuconfig
   CROSS_COMPILE=aarch64-poky-linux- make savedefconfig

We have save a.patch on Yocto's files folder. 
 
   mv configs/socfpga_stratix10_defconfig configs/socfpga_stratix10_defconfig_
   cp defconfig configs/socfpga_stratix10_defconfig 
   git diff configs/socfpga_stratix10_defconfig > socfpga_stratix10_defconfig.patch
   cp socfpga_stratix10_defconfig.patch $TOP_FOLDER/gsrd_socfpga/meta-intel-fpga-refdes/recipes-bsp/u-boot/files/ 
   mv configs/socfpga_stratix10_defconfig_ configs/socfpga_stratix10_defconfig

Now lets add an entry on the current .bbapend( at this time it would be $TOP_FOLDER/gsrd_socfpga/meta-intel-fpga-refdes/recipes-bsp/u-boot/u-boot-socfpga_v2021.10.bbappend). Locate the following lines: 

 
SRC_URI += "\
             file://0001-arm-Add-dwarf-4-to-compilation-flag.patch \
             file://0001-arm-agilex-add-patch-to-enable-board-3-PR-configurat.patch \ 
           "

to be 
 
SRC_URI += "\
             file://0001-arm-Add-dwarf-4-to-compilation-flag.patch \
             file://0001-arm-agilex-add-patch-to-enable-board-3-PR-configurat.patch \
             file://socfpga_stratix10_defconfig.patch    \   
           "

U-boot source:

Pretty similar to prior instructions. First we have to create a patch file. In this case it is recommendable to create a patch only for the files we modify. An example of this would be: 

   

  git diff arch/arm/dts/socfpga_stratix10_socdk.dts > socfpga_stratix10_socdk.dts.patch

Once we have a.patch. Let's copy it to Yocto's files folder. 
 

   cp socfpga_stratix10_defconfig.patch $TOP_FOLDER/gsrd_socfpga/meta-intel-fpga-refdes/recipes-bsp/u-boot/files/

Now lets add an entry on the current .bbapend( at this time it would be $TOP_FOLDER/gsrd_socfpga/meta-intel-fpga-refdes/recipes-bsp/u-boot/u-boot-socfpga_v2021.10.bbappend). Locate the following lines: 

 
SRC_URI += "\
             file://0001-arm-Add-dwarf-4-to-compilation-flag.patch \
             file://0001-arm-agilex-add-patch-to-enable-board-3-PR-configurat.patch \ 
           "

to be 
 
SRC_URI += "\
             file://0001-arm-Add-dwarf-4-to-compilation-flag.patch \
             file://0001-arm-agilex-add-patch-to-enable-board-3-PR-configurat.patch \
             file:// socfpga_stratix10_socdk.dts.patch  \   
           "

Build

Start building 
 bitbake u-boot-socfpga

Package

Once we have our modified and built U-boot we have to package it. 
 package

Reconfiguring Core Fabric from U-Boot

The GSRD configures the FPGA core fabric only once, from U-Boot, by using the bootm command.

Important : If the FPGA fabric is already configured and bridges are enabled, you must call the bridge disable command from U-Boot before issuing the bootm or fppga load commands to reconfigure the fabric. Only do this if you are using an arm-trusted-firmware version more recent than the following:

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