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Stratix 10 SoC H-Tile GSRD
Golden System Reference Design for Stratix 10 SX SoC Development Kit H-Tile

06 April 2024 - 01:39 | Release 24.1 | Radu Bacrau | GHRD, GSRD, H-Tile, Linux, Stratix 10 SoC, Yocto

Overview
Building the SD Card Version
Reconfiguring Core Fabric from U-Boot

Overview

The Stratix 10 SX SoC Development Kit H-Tile and Stratix 10 SX SoC Development Kit L-Tile are very similar boards, as documented at Intel Stratix 10 SX SoC Development Kit.

A full GSRD (Golden System Reference Design) is provided for the L-Tile version at Stratix 10 SoC L-Tile GSRD, including prebuilt binaries, instructions on how to use it, and instructions on how to rebuild it.

This page offers instructions on how to to build the H-Tile version of the GSRD for booting from SD card. Refer to Stratix 10 SoC L-Tile GSRD for instructions on how to build the rest of the scenarios, exercise the GSRD features, and customization. No prebuilt binaries are provided for the H-Tile version.

Prerequisites

The following are required in order to be able to fully exercise the S10 GSRD:

Stratix 10 SoC Development Kit, production version, H-Tile (ordering code DK-SOC-1SSX-H-D)
- 4GB DDR4 HILO memory card
- SD/MMC HPS Daughtercard
- SDM QSPI Bootcard(MT25QU02G)
- Mini USB cable for serial output
- Micro USB cable for on-board Intel FPGA Download Cable II
Micro SD card (4GB or greater)
Host PC with
- Linux - Ubuntu 22.04 was used to create this page, other versions and distributions may work too
- Serial terminal (for example Minicom on Linux and TeraTerm or PuTTY on Windows)
- Micro SD card slot or Micro SD card writer/reader
- Intel Quartus Prime Pro Edition
  - v24.1 for the prebuilt binaries
  - v24.1 for rebuilding the binaries
Local Ethernet network, with DHCP server (will be used to provide IP address to the board)

Component Versions

Quartus Prime Pro v24.1 and the following software component versions are used to build the GSRD:

Component	Location	Branch	Commit ID/Tag
GHRD	https://github.com/altera-opensource/ghrd-socfpga	master	QPDS24.1_REL_GSRD_PR
Linux	https://github.com/altera-opensource/linux-socfpga	socfpga-6.1.68-lts	QPDS24.1_REL_GSRD_PR
Arm Trusted Firmware	https://github.com/arm-trusted-firmware	socfpga_v2.10.0	QPDS24.1_REL_GSRD_PR
U-Boot	https://github.com/altera-opensource/u-boot-socfpga	socfpga_v2023.10	QPDS24.1_REL_GSRD_PR
Yocto Project	https://git.yoctoproject.org/poky	nanbield	latest
Yocto Project: meta-intel-fpga	https://git.yoctoproject.org/meta-intel-fpga	nanbield	latest
Yocto Project: meta-intel-fpga-refdes	https://github.com/altera-opensource/meta-intel-fpga-refdes	nanbield	QPDS24.1_REL_GSRD_PR

Release Notes

The Intel FPGA HPS Embedded Software release notes can be accessed from the following link: https://www.rocketboards.org/foswiki/Documentation/IntelFPGAHPSEmbeddedSoftwareRelease

Building the SD Card Version

Build Flow

The following diagram illustrates the full build flow for the GSRD based on source code from GitHub.

The current build flow creates a single boot image which is able to boot in different board configurations (either using OOBE or eMMC/NAND daughter card). For more information about how this single boot image is created, please refer to the following article: https://rocketboards.org/foswiki/Documentation/SingleImageBoot

Setting up Environment

Create a top folder for this example, as the rest of the commands assume this location:

sudo rm -rf stratix10_gsrd
mkdir stratix10_gsrd
cd stratix10_gsrd
export TOP_FOLDER=$(pwd)

Download the compiler toolchain, add it to the PATH variable, to be used by the GHRD makefile to build the HPS Debug FSBL:

cd $TOP_FOLDER
wget https://developer.arm.com/-/media/Files/downloads/gnu/11.2-2022.02/binrel/\
gcc-arm-11.2-2022.02-x86_64-aarch64-none-linux-gnu.tar.xz
tar xf gcc-arm-11.2-2022.02-x86_64-aarch64-none-linux-gnu.tar.xz
rm -f gcc-arm-11.2-2022.02-x86_64-aarch64-none-linux-gnu.tar.xz
export PATH=`pwd`/gcc-arm-11.2-2022.02-x86_64-aarch64-none-linux-gnu/bin:$PATH
export ARCH=arm64
export CROSS_COMPILE=aarch64-none-linux-gnu-

Enable Quartus tools to be called from command line:

export QUARTUS_ROOTDIR=~/intelFPGA_pro/24.1/quartus/
export PATH=$QUARTUS_ROOTDIR/bin:$QUARTUS_ROOTDIR/linux64:$QUARTUS_ROOTDIR/../qsys/bin:$PATH

Building the Hardware Design

cd $TOP_FOLDER
rm -rf ghrd-socfpga s10_soc_devkit_ghrd
git clone -b QPDS24.1_REL_GSRD_PR https://github.com/altera-opensource/ghrd-socfpga
mv ghrd-socfpga/s10_soc_devkit_ghrd .
rm -rf ghrd-socfpga
cd s10_soc_devkit_ghrd
export QUARTUS_DEVICE=1SX280HU2F50E1VGAS
make scrub_clean_all
make generate_from_tcl
make all
unset QUARTUS_DEVICE
cd ..

The following files are created in $TOP_FOLDER/s10_soc_devkit_ghrd/output_files:

ghrd_1sx280hu2f50e1vgas.sof - FPGA SOF file, without HPS FSBL
ghrd_1sx280hu2f50e1vgas_hps_debug.sof - FPGA SOF, with HPS Debug FSBL
ghrd_1sx280hu2f50e1vgas.pr_partition_0.rbf - PR bitsream for the baseline persona
alternate_persona.pr_partition_0.rbf - PR bitstream for the alternate persona

Building Core RBF

Create the Core RBF file to be used in the rootfs created by Yocto by using the HPS Debug SOF built by the GHRD makefile:

cd $TOP_FOLDER
quartus_pfg -c s10_soc_devkit_ghrd/output_files/ghrd_1sx280hu2f50e1vgas_hps_debug.sof \
  ghrd_1sx280hu2f50e1vgas.jic \
  -o device=MT25QU02G \
  -o flash_loader=1SX280HU2F50E1VGAS \
  -o mode=ASX4 \
  -o hps=1
rm ghrd_1sx280hu2f50e1vgas.hps.jic

The following files will be created:

$TOP_FOLDER/ghrd_1sx280hu2f50e1vgas.core.rbf - HPS First configuration bitstream, phase 2: FPGA fabric

Note we are also creating an HPS JIC file, but we are discarding it, as it has the HPS Debug FSBL, while the final image needs to have the U-Boot SPL created by the Yocto recipes.

Setting Up Yocto Build System

1. First, make sure you have Yocto system requirements met: https://docs.yoctoproject.org/3.4.1/ref-manual/system-requirements.html#supported-linux-distributions.

The command to install the required packages on Ubuntu 20.04 is:

sudo apt-get update
sudo apt-get upgrade
sudo apt-get install openssh-server mc libgmp3-dev libmpc-dev gawk wget git diffstat unzip texinfo gcc \
build-essential chrpath socat cpio python3 python3-pip python3-pexpect xz-utils debianutils iputils-ping \
python3-git python3-jinja2 libegl1-mesa libsdl1.2-dev pylint3 xterm python3-subunit mesa-common-dev zstd \
liblz4-tool git fakeroot build-essential ncurses-dev xz-utils libssl-dev bc flex libelf-dev bison xinetd \
tftpd tftp nfs-kernel-server libncurses5 libc6-i386 libstdc++6:i386 libgcc++1:i386 lib32z1 \
device-tree-compiler curl mtd-utils u-boot-tools net-tools swig -y

On Ubuntu 20.04 you will also need to point the /bin/sh to /bin/bash, as the default is a link to /bin/dash:

 sudo ln -sf /bin/bash /bin/sh

Note: You can also use a Docker container to build the Yocto recipes, refer to https://rocketboards.org/foswiki/Documentation/DockerYoctoBuild for details. When using a Docker container, it does not matter what Linux distribution or packages you have installed on your host, as all dependencies are provided by the Docker container.

2. Clone the Yocto script and prepare the build:

cd $TOP_FOLDER
rm -rf gsrd_socfpga
git clone -b nanbield https://github.com/altera-opensource/gsrd_socfpga
cd gsrd_socfpga
. stratix10-gsrd-build.sh
build_setup

Note: Run the following commands to set up again the yocto build environments, if you closed the current window (for example when rebooting the Linux host) and want to resume the next steps:

cd $TOP_FOLDER/gsrd_socfpga
. ./poky/oe-init-build-env stratix10-gsrd-rootfs/

Customize Yocto Build

1. Copy the rebuilt files to $WORKSPACE/meta-intel-fpga-refdes/recipes-bsp/ghrd/files using the following names, as expected by the yocto recipes:

stratix10_gsrd_ghrd.core.rbf
stratix10_nand_ghrd.core.rbf: not applicable, as we have not rebuilt the NAND version

This can be accomplished using the following instructions:

GHRD_LOC=$WORKSPACE/meta-intel-fpga-refdes/recipes-bsp/ghrd/files
CORE_RBF=$GHRD_LOC/stratix10_gsrd_ghrd.core.rbf
PER0_RBF=$GHRD_LOC/stratix10_pr_persona0.rbf 
PER1_RBF=$GHRD_LOC/stratix10_pr_persona1.rbf
cp $TOP_FOLDER/ghrd_1sx280hu2f50e1vgas.core.rbf $CORE_RBF
cp $TOP_FOLDER/s10_soc_devkit_ghrd/output_files/ghrd_1sx280hu2f50e1vgas.pr_partition_0.rbf $PER0_RBF
cp $TOP_FOLDER/s10_soc_devkit_ghrd/output_files/alternate_persona.pr_partition_0.rbf $PER1_RBF

2. Update the Yocto recipe at $WORKSPACE/meta-intel-fpga-refdes/recipes-bsp/ghrd/hw-ref-design.bb to change the SRC_URI:stratix10 from the orginal value:

SRC_URI:stratix10 ?= "\
      ${GHRD_REPO}/stratix10_gsrd_${ARM64_GHRD_CORE_RBF};name=stratix10_gsrd_core \
      ${GHRD_REPO}/stratix10_nand_${ARM64_GHRD_CORE_RBF};name=stratix10_nand_core \
      ${GHRD_REPO}/stratix10_pr_persona0.rbf;name=stratix10_pr_persona0 \
      ${GHRD_REPO}/stratix10_pr_persona1.rbf;name=stratix10_pr_persona1 \
      "

to be:

SRC_URI:stratix10 ?= "\
      file://stratix10_gsrd_ghrd.core.rbf \
      ${GHRD_REPO}/stratix10_nand_${ARM64_GHRD_CORE_RBF};name=stratix10_nand_core \
      file://stratix10_pr_persona0.rbf \
      file://stratix10_pr_persona1.rbf \
      "

using the following commands from the console:

OLD_CORE_URI="\${GHRD_REPO}\/stratix10_gsrd_\${ARM64_GHRD_CORE_RBF};name=stratix10_gsrd_core"
NEW_CORE_URI="file:\/\/stratix10_gsrd_ghrd.core.rbf"
OLD_PER0_URI="\${GHRD_REPO}\/stratix10_pr_persona0.rbf;name=stratix10_pr_persona0"
NEW_PER0_URI="file:\/\/stratix10_pr_persona0.rbf"
OLD_PER1_URI="\${GHRD_REPO}\/stratix10_pr_persona1.rbf;name=stratix10_pr_persona1"
NEW_PER1_URI="file:\/\/stratix10_pr_persona1.rbf"
RECIPE=$WORKSPACE/meta-intel-fpga-refdes/recipes-bsp/ghrd/hw-ref-design.bb
sed -i "s/$OLD_CORE_URI/$NEW_CORE_URI/g" $RECIPE
sed -i "s/$OLD_PER0_URI/$NEW_PER0_URI/g" $RECIPE
sed -i "s/$OLD_PER1_URI/$NEW_PER1_URI/g" $RECIPE

Note we have left the NAND file alone, that will be downloaded from rocketboards.

3. Update the same Yocto recipe to change the SHA checksums for the new files:

SRC_URI[stratix10_gsrd_core.sha256sum] = "ea26a77ebc1b3141193de6dd32e22f332785e05c956de85118c3790392141d3c"
SRC_URI[stratix10_nand_core.sha256sum] = "d782c05085f8f13cb792b687fd002773e0897e4d7ecf5451994b1823d62cdc92"
SRC_URI[stratix10_pr_persona0.sha256sum] = "60af20604f8756b251d3bff23ceaf8c4edec6d37cf4558ed763e1e311ab4c81e"
SRC_URI[stratix10_pr_persona1.sha256sum] = "c555e432574431ec0d2596fe7dc3f4ace86899add91599023d26127a9d78293b"

to the new values using the following commands:

CORE_SHA=$(sha256sum $CORE_RBF | cut -f1 -d" ")
PER0_SHA=$(sha256sum $PER0_RBF | cut -f1 -d" ")
PER1_SHA=$(sha256sum $PER1_RBF | cut -f1 -d" ")
OLD_CORE_SHA="SRC_URI\[stratix10_gsrd_core\.sha256sum\] = .*"
NEW_CORE_SHA="SRC_URI[stratix10_gsrd_core.sha256sum] =  \"$CORE_SHA\""
OLD_PER0_SHA="SRC_URI\[stratix10_pr_persona0\.sha256sum\] = .*"
NEW_PER0_SHA="SRC_URI[stratix10_pr_persona0.sha256sum] =  \"$PER0_SHA\""
OLD_PER1_SHA="SRC_URI\[stratix10_pr_persona1\.sha256sum\] = .*"
NEW_PER1_SHA="SRC_URI[stratix10_pr_persona1.sha256sum] =  \"$PER1_SHA\""
sed -i "s/$OLD_CORE_SHA/$NEW_CORE_SHA/g" $RECIPE
sed -i "s/$OLD_PER0_SHA/$NEW_PER0_SHA/g" $RECIPE
sed -i "s/$OLD_PER1_SHA/$NEW_PER1_SHA/g" $RECIPE

4. Optionally change the following files in $WORKSPACE/meta-intel-fpga-refdes/recipes-bsp/u-boot/files/:

uboot.txt - distroboot script
uboot_script.its - its file for creating FIT image from the above script

5. Optionally change the following file in $WORKSPACE/meta-intel-fpga-refdes/recipes-kernel/linux/linux-socfpga-lts:

fit_kernel_stratix10.its - its file for creating the kernel.itb image, containing by default:
- Kernel
- Device trees for SD and NAND board configurations
- Core RBF files for SD and NAND board configurations
- Board configurations for SD and NAND cases

Build Yocto

Build Yocto:

bitbake_image

Gather files:

package

Once the build is completed successfully, you will see the following two folders are created:

stratix10_gsrd_rootfs: area used by OpenEmbedded build system for builds. Description of build directory structure - https://docs.yoctoproject.org/ref-manual/structure.html#the-build-directory-build
stratix10_gsrd_images: the build script copies here relevant files built by Yocto from the stratix10_gsrd_rootfs/tmp/deploy/images/agilex folder, but also other relevant files.

The two most relevant files created in the $TOP_FOLDER/gsrd_socfpga/stratix10-gsrd-images folder are:

File	Description
sdimage.tar.gz	SD Card Image
u-boot-stratix10-socdk-gsrd-atf/u-boot-spl-dtb.hex	U-Boot SPL Hex file

Building QSPI Flash Image

The QSPI image will contain the FPGA configuration data and the HPS FSBL and it can be built using the following command:

cd $TOP_FOLDER
quartus_pfg -c s10_soc_devkit_ghrd/output_files/ghrd_1sx280hu2f50e1vgas.sof \
  ghrd_1sx280hu2f50e1vgas.jic \
  -o device=MT25QU02G \
  -o flash_loader=1SX280HU2F50E1VGAS \
  -o hps_path=gsrd_socfpga/stratix10-gsrd-images/u-boot-stratix10-socdk-gsrd-atf/u-boot-spl-dtb.hex \
  -o mode=ASX4 \
  -o hps=1

The following files will be created:

$TOP_FOLDER/ghrd_1sx280hu2f50e1vgas.hps.jic - Flash image for HPS First configuration bitstream, phase 1: HPS and DDR
$TOP_FOLDER/ghrd_1sx280hu2f50e1vgas.core.rbf - HPS First configuration bitstream, phase 2: FPGA fabric. We already have the same file on the SD card.

Booting Linux

1. Write SD card image

2. Write QSPI image

3. Power cycle board

4. Linux will boot up, use 'root' as username, no password will be required:

U-Boot SPL 2023.10 (Mar 21 2024 - 07:41:59 +0000)
Reset state: Cold
MPU         1200000 kHz
L3 main     400000 kHz
Main VCO    2400000 kHz
Per VCO     2000000 kHz
EOSC1       25000 kHz
HPS MMC     50000 kHz
UART        100000 kHz
DDR: 4096 MiB
SDRAM-ECC: Initialized success with 986 ms
QSPI: Reference clock at 400000 kHz
WDT:   Started watchdog@ffd00200 with servicing every 1000ms (10s timeout)
denali-nand-dt nand@ffb90000: timeout while waiting for irq 0x2000
denali-nand-dt nand@ffb90000: reset not completed.
Trying to boot from MMC1
## Checking hash(es) for config board-4 … OK
## Checking hash(es) for Image atf … crc32+ OK
## Checking hash(es) for Image uboot … crc32+ OK
## Checking hash(es) for Image fdt-0 … crc32+ OK
NOTICE:  BL31: v2.10.0	(release):QPDS24.1_REL_GSRD_PR
NOTICE:  BL31: Built : 08:52:03, Mar 21 2024

U-Boot 2023.10 (Mar 21 2024 - 07:41:59 +0000)socfpga_stratix10

CPU:   Intel FPGA SoCFPGA Platform (ARMv8 64bit Cortex-A53)
Model: SoCFPGA Stratix 10 SoCDK
DRAM:  2 GiB (effective 4 GiB)
Core:  27 devices, 22 uclasses, devicetree: separate
WDT:   Started watchdog@ffd00200 with servicing every 1000ms (10s timeout)
NAND:  denali-nand-dt nand@ffb90000: timeout while waiting for irq 0x2000
denali-nand-dt nand@ffb90000: reset not completed.
Failed to initialize Denali NAND controller. (error -5)
0 MiB
MMC:   dwmmc0@ff808000: 0
Loading Environment from FAT... Unable to read "uboot.env" from mmc0:1...
Loading Environment from UBI... denali-nand-dt nand@ffb90000: timeout while waiting for irq 0x2000
denali-nand-dt nand@ffb90000: reset not completed.
SF: Detected mt25qu02g with page size 256 Bytes, erase size 64 KiB, total 256 MiB
Could not find a valid device for ffb90000.nand.0
Volume env not found!

** Unable to read env from root:env **
In:    serial0@ffc02000
Out:   serial0@ffc02000
Err:   serial0@ffc02000
Net:   
Warning: ethernet@ff800000 (eth0) using random MAC address - 76:7d:51:ae:41:35
eth0: ethernet@ff800000
Hit any key to stop autoboot:  5  4  3  2  1  0 
switch to partitions #0, OK
mmc0 is current device
Scanning mmc 0:1...
Found U-Boot script /boot.scr.uimg
2411 bytes read in 3 ms (784.2 KiB/s)
## Executing script at 05ff0000
crc32+ Trying to boot Linux from device mmc0
Found kernel in mmc0
17181811 bytes read in 785 ms (20.9 MiB/s)
## Loading kernel from FIT Image at 01000000 …
   Using 'board-4' configuration
   Verifying Hash Integrity … OK
   Trying 'kernel' kernel subimage
     Description:  Linux Kernel
     Type:         Kernel Image
     Compression:  lzma compressed
     Data Start:   0x010000dc
     Data Size:    9521379 Bytes = 9.1 MiB
     Architecture: AArch64
     OS:           Linux
     Load Address: 0x06000000
     Entry Point:  0x06000000
     Hash algo:    crc32
     Hash value:   474b072b
   Verifying Hash Integrity … crc32+ OK
## Loading fdt from FIT Image at 01000000 …
   Using 'board-4' configuration
   Verifying Hash Integrity … OK
   Trying 'fdt-4' fdt subimage
     Description:  socfpga_socdk_combined
     Type:         Flat Device Tree
     Compression:  uncompressed
     Data Start:   0x019253b0
     Data Size:    36985 Bytes = 36.1 KiB
     Architecture: AArch64
     Hash algo:    crc32
     Hash value:   9dd4ce96
   Verifying Hash Integrity … crc32+ OK
   Booting using the fdt blob at 0x19253b0
Working FDT set to 19253b0
## Loading fpga from FIT Image at 01000000 …
   Trying 'fpga-4' fpga subimage
     Description:  FPGA bitstream for GHRD
     Type:         FPGA Image
     Compression:  uncompressed
     Data Start:   0x01ccd59c
     Data Size:    3756032 Bytes = 3.6 MiB
     Load Address: 0x0a000000
     Hash algo:    crc32
     Hash value:   f5e36e91
   Verifying Hash Integrity … crc32+ OK
   Loading fpga from 0x01ccd59c to 0x0a000000
….FPGA reconfiguration OK!
Enable FPGA bridges
   Programming full bitstream... OK
   Uncompressing Kernel Image
   Loading Device Tree to 000000007eac9000, end 000000007ead5078 … OK
Working FDT set to 7eac9000
Removing MTD device #2 (root) with use count 1
Error when deleting partition "root" (-16)
SF: Detected mt25qu02g with page size 256 Bytes, erase size 64 KiB, total 256 MiB
Enabling QSPI at Linux DTB...
Working FDT set to 7eac9000
libfdt fdt_path_offset() returned FDT_ERR_NOTFOUND
libfdt fdt_path_offset() returned FDT_ERR_NOTFOUND
QSPI clock frequency updated
RSU: Firmware or flash content not supporting RSU
RSU: Firmware or flash content not supporting RSU
RSU: Firmware or flash content not supporting RSU
RSU: Firmware or flash content not supporting RSU

Starting kernel …

Deasserting all peripheral resets
[    0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034]
[    0.000000] Linux version 6.1.68-altera (oe-user@oe-host) (aarch64-poky-linux-gcc (GCC) 13.2.0, GNU ld (GNU Binutils) 2.41.0.20231213) #1 SMP PREEMPT Thu Mar 28 07:56:27 UTC 2024
[    0.000000] Machine model: SoCFPGA Stratix 10 SoCDK

…

[    9.533171] socfpga-dwmac ff804000.ethernet eth2: registered PTP clock
[    9.540304] socfpga-dwmac ff804000.ethernet eth2: configuring for phy/sgmii link mode
[   13.284366] socfpga-dwmac ff800000.ethernet eth0: Link is Up - 1Gbps/Full - flow control rx/tx
[   13.293038] IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready

Poky (Yocto Project Reference Distro) 4.3.4 stratix10 ttyS0

stratix10 login: [   14.884095] 8021q: 802.1Q VLAN Support v1.8
root

root@stratix10:~#

Reconfiguring Core Fabric from U-Boot

The GSRD configures the FPGA core fabric only once, from U-Boot, by using the bootm command.

Important : If the FPGA fabric is already configured and bridges are enabled, you must call the bridge disable command from U-Boot before issuing the bootm or fppga load commands to reconfigure the fabric. Only do this if you are using an arm-trusted-firmware version more recent than the following:

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Stratix 10 SoC H-Tile GSRD Golden System Reference Design for Stratix 10 SX SoC Development Kit H-Tile