Introduction

In order to enable boot from FPGA in the GHRD, changes below are required.

• The FPGA on chip RAM contains a compiled U-boot in .hex format.
• The HPS instance includes boot from FPGA signals.
• The FPGA top level drives the boot from FPGA signals.

Editing the GHRD Hardware Design for FPGA boot

Please refer to section “1. Editing the GHRD Hardware Design for FPGA boot” in link below.

https://rocketboards.org/foswiki/view/Documentation/A10GSRD151FPGABoot

There is additional settings required in A10 GHRD so the boot from FPGA can work correctly. Select “Enable boot selection from FPGA”, and confirming “FPGA” is selected from “Boot selection from FPGA” drop down list.

Boot Loader Generation: u-boot-socfpga

1. Open SoC EDS embedded_command_shell.sh

% <path>/altera/17.1/embedded/embedded_command_shell.sh

2. Open bsp-editor

% bsp-editor

3. Create a new HPS bsp via File menu → New HPS BSP.

4. Point to the software hand off directory (hps_isw_handoff) created from the Quartus compilation and click OK.

5. Edit the BSP and select external_fpga_config and boot from SD/MMC or boot from QSPI. With these selections, the U-boot compilation will include the SD/MMC drivers, allowing use of the SD/MMC flash in U-Boot.

6. Click Generate then Exit. This will copy the u-boot-socfpga from SoC EDS directory to bsp directory.

7. Navigate to the location of the created u-boot in your terminal.

% cd <path>/software/<BSP name>

8. Open the device tree file devicetree.dts, and add a config section below the chosen {} section to disable u-boot from loading its environment from a flash device.

chosen{
        /* Bootloader setting: uboot.external_fpga_config */
        external-fpga-config;
        };
        config {
        load-environment=<0>;
        };

9. Build U-boot by running make command.

% make

10. Edit the u-boot configuration file for the Arria 10 SoC /uboot-socfpga/include/configs/socfpga_arria10.h to define CONFIG_UBOOT_EXE_ON_FPGA as 1 so that the text base location of uboot is the base of the on-chip RAM on the H2F bridge (0xC0000000).

#ifndef CONFIG_UBOOT_EXE_ON_FPGA
#define CONFIG_UBOOT_EXE_ON_FPGA    1
#endif

/* Base address for .text section. */
/* Ensure located start of FPGA OCRAM */
#if (1 == CONFIG_UBOOT_EXE_ON_FPGA)
#define CONFIG_SYS_TEXT_BASE         0xc0000000
#else
/* Ensure located start of HPS OCRAM */
#define CONFIG_SYS_TEXT_BASE         0xFFE00000
#endif

11. (Optional) Edit the u-boot configuration file for Arria 10 SoC to set the MAC address for the Ethernet IP in the default environment in /uboot-socfpga/include/configs/socfpga_arria10.h. Add an entry for ethaddr as follows. Replace <XX:XX:XX:XX:XX:XX> with a with a 12 character hex string of the format XX:XX:XX:XX:XX:XX

#define CONFIG_EXTRA_ENV_SETTINGS \
"verify=y\0" \
"ethaddr=<XX:XX:XX:XX:XX:XX>\0" \
"loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \

12. Re-build U-Boot.

• Clean

% cd <path>/software/<BSP name>/
% make clean

• Make

% make

13. Convert the generated preloader image uboot_w_dtb-mkpimage.bin to Intel .hex format for loading into the FPGA on chip RAM.

% arm-altera-eabi-objcopy -I binary -O ihex --adjust-vma -0x00000000 u-boot_w_dtb.bin hpsBootTarget.hex

Updating the Qsys Project

Please refer to section “3. Updating the Qsys project” in link below.

https://rocketboards.org/foswiki/view/Documentation/A10GSRD151FPGABoot

Optional: MIF Update Flow

Please refer to section “4. Optional: MIF Update Flow” in link below.

https://rocketboards.org/foswiki/view/Documentation/A10GSRD151FPGABoot

Optional: Convert the Programming File to RBF Format

Please refer to section “5. Optional: Convert the programming file to RBF format” in link below.

https://rocketboards.org/foswiki/view/Documentation/A10GSRD151FPGABoot

Configuring the Board for FPGA Boot

Please refer to section “6. Configuring the board for FPGA boot” in link below.

https://rocketboards.org/foswiki/view/Documentation/A10GSRD151FPGABoot

Test the System

Please refer to “7. Test the system” in link below for details.

https://rocketboards.org/foswiki/view/Documentation/A10GSRD151FPGABoot