Reference Design on Stratix 10 Development Kit demonstrating a Gen3x8 Capable Root Port
Summary
This reference design demonstrates a PCIe root port running on Stratix 10 SoC Development Kit connected to Intel SSD DC P3500 Non-Volatile Memory express (NVMe) end point. A Gen3 x8 PCIe link is shown.
The root port reference design is based on the Stratix 10 Golden System Reference Design, with PCIe root port and necessary Linux software infrastructure added.
Required Components
- Root Port Host Board
- Example End Points
- Pre-compiled Software/Firmware
- Tools and Software
- Linux Development Computer (Ubuntu, CentOS, or similar) with a SD Card reader
- Quartus Pro 19.3
- Linux kernel 4.14.130-ltsi
- A serial terminal application, such as TeraTerm, Putty or Minicom
Helpful Reference Documentation
Release Contents
The PCIe RP reference design sources and prebuilt binaries can be downloaded from
here.
Hardware Description
Root Port Design
The root port reference design hardware is shown in the diagram below. This design is based on the Stratix 10 SoC Development Kit Golden Hardware Reference Design (GHRD), which is part of the Golden System Reference Design (GSRD). A PCIe Root Port Subsystem and 256kB on chip RAM have been added. Please refer to the QSYS files included with the Root Port Hardware Design (listed in the
Build Stratix 10 PCIe Root Port and Integrating U-boot FSBL section below) for further detail. A few more components, such as performance counter and JTAG Avalon Masters, have been added to the design for debug and benchmarking but are not shown here.
AXI-4 to ACE-lite Accelerator Coherency Port Bridge
AXI-4 to ACE-lite Accelerator Coherency Port Bridge is a custom IP block created for coherent access. This block fixed ACE-LITE interface with values below:
| AWSNOOP[2:0] |
AWDOMAIN[1:0] |
AWBAR[1:0] |
Transaction Type |
|---|
| 3'b000 |
2b'10 |
2'b00 |
WriteUnique |
| ARSNOOP[3:0] |
ARDOMAIN[1:0] |
ARBAR[1:0] |
Transaction Type |
|---|
| 4'b0000 |
2'b10 |
2'b00 |
ReadOnce |
| AWCACHE[3:0] |
ARCACHE[3:0] |
Memory Type |
|---|
| 4'b1111 |
4'b1111 |
Write-back Read and Write-allocate |
| AWPROT[2:0] |
ARPROT[2:0] |
|---|
| 3'b011 |
3'b011 |
WriteUnique - Uncached masters writing shared data, all other cached copies must be cleaned. Any dirty copy must be written to memory and clean copies invalidated.
ReadOnce - Master reads data that is shared but where the master will not retain a copy, meaning that other masters with a cached copy do not need to change cache state.
Write-back Read and Write-allocate
Write-back - Data is written only to the block in the cache upon cache hit. The modified cache block is written to main memory only when it is replaced.
Read and write-allocate - Cache block will be allocated for read or write upon cache miss. Data is loaded from memory into the cache block. For write, new data is written into the cache block.
Memory Map
HPS LWH2F Memory Map | Address Offset |
Size (Bytes) |
Peripheral |
Remarks |
|---|
| 0xF9000000 |
8 |
System ID |
Hardware configuration system ID |
| 0xF9001080 |
16 |
LED PIO |
|
| 0xF9001060 |
16 |
Button PIO |
Push Button |
| 0xF9001070 |
16 |
DIPSW PIO |
DIP Switch |
| 0xF9001100 |
256 |
ILC |
Interrupt Latency Counter |
| 0xF9010000 |
32k |
PCIe CRA |
Avalon MM Slave of PCIe HIP CRA port |
| 0xF9018000 |
128 |
MSI-to-GIC Vector |
|
| 0xF9018080 |
16 |
MSI-to-GIC CSR |
Avalon MM Slave of MSI-to-GIC CSR port |
| 0xF90180a0 |
32 |
Performance Counter |
Hardware timer for benchmarking purposes |
HPS H2F Memory Map | Address Offset |
Size (Bytes) |
Peripheral |
Remarks |
|---|
| 0x80000000 |
256k |
On Chip Memory |
Block memory implemented in the FPGA fabric |
| 0x90000000 |
256M |
PCIe HPTXS |
Avalon MM Slave of PCIe HIP HPTXS port |
| 0xA0000000 |
2M |
PCIe HIP Reconfig |
Avalon MM Slave of PCIe HIP Reconfig port |
PCIe HIP BAR0 Memory Map | Address Offset |
Size (Bytes) |
Peripheral |
Remarks |
|---|
| 0x80000000 |
256k |
On Chip Memory |
Block memory implemented in the FPGA fabric |
| 0xF9018000 |
128 |
MSI-to-GIC Vector |
|
| 0x00000000 |
4G |
HPS F2H |
|
Intel SSD DC P3500 Non-Volatile Memory express (NVMe) End Point
Intel SSD DC P3500 Non-Volatile Memory express (NVMe) is an Intel Solid State Drive (SSD) Data Center family for PCIe supporting PCIe 3.0 x 4 that brings extreme data throughput. More information about Intel SSD DC P3500 NVMe can be found
here.
Hardware Setup
Configure switches on the board as below:
- SW1: OFF-ON-ON-ON-ON-ON-ON-ON
- SW2: All ON
- SW3: All OFF
- SW4: ON-OFF-ON-OFF
Attach an OOBE Daughter Card to J15 on the Stratix 10 SoC Development Kit. Connect micro USB cable between host PC and micro USB port (J57) on the board and connect mini USB cable from host computer to mini USB port (J7) on the OOBE Daughter Card.
The Stratix 10 Root Port Reference Design can be run with Intel SSD DC P3500 NVMe End Point.
Setup Intel SSD DC P3500 NVMe End Point
Just insert Intel SSD DC P3500 NVMe end point card into the PCIe slot on Stratix 10 SoC Development Kit.
Create SD Card for Stratix 10 SoC Development Kit
This section describes how to create a SD Card that contains the default pre-built version of this reference design. Please refer to the for instructions on how to completely rebuild all the individual components in SD card image, including the bootloader and root file system, from scratch.
On a Linux machine,
- 1.) Download the sdimage.tar.gz listed in the Release Contents section above.
- 2.) Run tar xvfz sdimage.tar.gz to extract the SD Card binary image (sdimage.img).
- 3.) Insert the SD Card to be updated into an SD Card reader attached to the computer.
- 4.) Use dd if=sdimage.img of=/dev/{sdcard} to copy the SD Card binary image to the SD Card device.
Booting the System
Option 1: Programming *.sof file Using JTAG Configuration
Note: .sof need to be programmed every time when board is powered up
- Please make sure switches on the Stratix 10 Soc Development Kit are configured as below.
- SW1: OFF-ON-ON-ON-ON-ON-ON-ON
- SW2: All ON
- SW3: All OFF
- SW4: ON-OFF-ON-OFF
- With the board powered down, insert the SD Card created above into the SD Card slot.
- Connect micro USB cable between host PC and micro USB port (J57) on the board and connect mini USB cable between host PC and mini USB port (J7) on OOBE Daughter Card.
- Power on the Stratix 10 SoC Development Kit and open a serial port terminal application on the host PC such as TeraTerm, Putty, Minicom on host PC with settings below.
- Baud-rate: 115,200
- Parity: none
- Flow control: none
- Stop bits: 1
- Open Quartus Prime Programmer and select Stratix 10L SoC Dev Kit for the Hardware Setup.
- Click Auto Detect to detect the Stratix 10 SoC device in the JTAG scan chain.
- Select the 1SX280LU2F50S2 device and click on Change File.
- Navigate to the location of the pre-built sof file and click OK.
- Check the Program/Configure checkbox. Click Start to begin configuring the device.
Option 2: Programming the Active Serial/QSPI Flash Using *.jic file
Note: .jic only need to be programmed once as the configuration image is stored in flash
- Please make sure switches on the Stratix 10 Soc Development Kit are configured as below.
- SW1: OFF-ON-ON-ON-ON-ON-ON-ON
- SW2: All ON
- SW3: All OFF
- SW4: ON-OFF-ON-OFF
- With the board powered down, insert the SD Card created above into the SD Card slot.
- Connect micro USB cable between host PC and micro USB port (J57) on the board and connect mini USB cable between host PC and mini USB port (J7) on OOBE Daughter Card.
- Power on the Stratix 10 SoC Development Kit and open a serial port terminal application on the host PC such as TeraTerm, Putty, Minicom on host PC with settings below.
- Baud-rate: 115,200
- Parity: none
- Flow control: none
- Stop bits: 1
- Open Quartus Prime Programmer and select Stratix 10L SoC Dev Kit for the Hardware Setup.
- Click Auto Detect to detect the Stratix 10 SoC device in the JTAG scan chain.
- Select the 1SX280LU2F50S2 device and click on Change File.
- Navigate to the location of the pre-built jic file and click OK.
- Check the Program/Configure checkbox. Optionally, click the Verify checkbox to verify the content after programming. Click Start to begin configuring the device.
- Once the programming is complete, power down the board. Change the MSEL[2:0] to 001 (Active Serial Fast mode) so that the Stratix 10 SoC device can boot from QSPI flash. It can be done by setting the SW2 to configuration below.
You should see the U-Boot bootloader start...
U-Boot SPL 2019.04-00262-ga54da27-dirty (Feb 14 2020 - 15:57:48 +0800)
MPU 1000000 kHz
L3 main 400000 kHz
Main VCO 2000000 kHz
Per VCO 2000000 kHz
EOSC1 25000 kHz
HPS MMC 50000 kHz
UART 100000 kHz
DDR: 4096 MiB
SDRAM-ECC: Initialized success with 1105 ms
QSPI: Reference clock at 400000000 Hz
Trying to boot from MMC1
U-Boot 2019.04-00262-ga54da27-dirty (Feb 14 2020 - 16:38:15 +0800)socfpga_stratix10
CPU: Intel FPGA SoCFPGA Platform (ARMv8 64bit Cortex-A53)
Model: SoCFPGA Stratix 10 SoCDK
DRAM: 4 GiB
MMC: dwmmc0@ff808000: 0
Loading Environment from MMC... *** Warning - bad CRC, using default environment
In: serial0@ffc02000
Out: serial0@ffc02000
Err: serial0@ffc02000
Net:
Warning: ethernet@ff800000 (eth0) using random MAC address - 66:f2:57:df:52:c6
eth0: ethernet@ff800000
Hit any key to stop autoboot: 5
Next, you should see the system booting into Linux
349 bytes read in 2 ms (169.9 KiB/s)
## Executing script at 02100000
17457664 bytes read in 790 ms (21.1 MiB/s)
16981 bytes read in 2 ms (8.1 MiB/s)
SF: Detected mt25qu02g with page size 256 Bytes, erase size 4 KiB, total 256 MiB
Enabling QSPI at Linux DTB...
RSU: Firmware or flash content not supporting RSU
## Flattened Device Tree blob at 08000000
Booting using the fdt blob at 0x8000000
Loading Device Tree to 000000007fa34000, end 000000007fa3bfff ... OK
Starting kernel ...
Deasserting all peripheral resets
[ 0.000000] Booting Linux on physical CPU 0x0
[ 0.000000] Linux version 4.14.130-ltsi-altera (limweili@pg-iccf0305) (gcc version 7.3.1 20180425 [linaro-7.3-2018.05 revision d29120a424ecfbc167ef90065c0eeb7f91977701] (Linaro GCC 7.3-2018.05)) #3 SMP PREEMPT Fri Feb 28 14:50:00 +08 2020
[ 0.000000] Boot CPU: AArch64 Processor [410fd034]
(........)
[ OK ] Started Serial Getty on ttyS0.
[ 6.428546] socfpga-dwmac ff800000.ethernet eth0: registered PTP clock
[ OK [ 6.450748] IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
] Started Getty on tty1.
[ OK ] Reached target Login Prompts.
[ OK ] Started NFS status monitor for NFSv2/3 locking..
[ OK ] Started WPA supplicant.
[ OK ] Started Hostname Service.
.---O---.
| | .-. o o
| | |-----.-----.-----.| | .----..-----.-----.
| | | __ | ---'| '--.| .-'| | |
| | | | | |--- || --'| | | ' | | | |
'---'---'--'--'--. |-----''----''--' '-----'-'-'-'
-' |
'---'
The Angstrom Distribution stratix10 ttyS0
Angstrom v2019.06 - Kernel
stratix10 login:
Once the system has booted into Linux, login by entering "root" as the username...
.---O---.
| | .-. o o
| | |-----.-----.-----.| | .----..-----.-----.
| | | __ | ---'| '--.| .-'| | |
| | | | | |--- || --'| | | ' | | | |
'---'---'--'--'--. |-----''----''--' '-----'-'-'-'
-' |
'---'
The Angstrom Distribution stratix10 ttyS0
Angstrom v2019.06 - Kernel
stratix10 login: root
Last login: Sat Sep 28 16:26:05 UTC 2019 on ttyS0
root@stratix10:~#
Intel SSD DC P3500 Non-Volatile Memory express (NVMe)
Firstly, check with "
lspci -v " command to make sure the Intel SSD DC P3500 NVMe is discovered by the PCIe root port and the proper Linux kernel modules have been loaded. Output as below.
root@stratix10:~# lspci -v
00:00.0 PCI bridge: Altera Corporation Device e000 (rev 01) (prog-if 00 [Normal decode])
Flags: bus master, fast devsel, latency 0, IRQ 59
Bus: primary=00, secondary=01, subordinate=01, sec-latency=0
I/O behind bridge: None
Memory behind bridge: 00000000-000fffff [size=1M]
Prefetchable memory behind bridge: None
Capabilities: [40] Power Management version 3
Capabilities: [50] MSI: Enable+ Count=1/4 Maskable+ 64bit+
Capabilities: [70] Express Root Port (Slot-), MSI 00
Capabilities: [100] Advanced Error Reporting
Capabilities: [148] Virtual Channel
Capabilities: [188] Secondary PCI Express <?>
Capabilities: [b80] Vendor Specific Information: ID=1172 Rev=0 Len=05c <?>
Kernel driver in use: pcieport
01:00.0 Non-Volatile memory controller: Intel Corporation PCIe Data Center SSD (rev 01) (prog-if 02 [NVM Express])
Subsystem: Intel Corporation DC P3500 SSD [Add-in Card]
Flags: bus master, fast devsel, latency 0, IRQ 58, NUMA node 0
Memory at 90010000 (64-bit, non-prefetchable) [size=16K]
[virtual] Expansion ROM at 90000000 [disabled] [size=64K]
Capabilities: [40] Power Management version 3
Capabilities: [50] MSI-X: Enable+ Count=32 Masked-
Capabilities: [60] Express Endpoint, MSI 00
Capabilities: [100] Advanced Error Reporting
Capabilities: [150] Virtual Channel
Capabilities: [180] Power Budgeting <?>
Capabilities: [190] Alternative Routing-ID Interpretation (ARI)
Capabilities: [270] Device Serial Number 55-cd-2e-40-4b-fc-20-c4
Capabilities: [2a0] Secondary PCI Express <?>
Kernel driver in use: nvme
Kernel modules: nvme
root@stratix10:~#
fio (flexible I/O tester) on NVMe
Run
fio (flexible I/O tester) test on NVMe with command below in Linux console.
WRITE : root@stratix10:~# fio --filename=/dev/nvme0n1 --rw=write --gtod_reduce=1 --blocksize=64k --size=2G --iodepth=2 --group_reporting --name=myjob --ioengine=libaio --numjobs=<no of job>
READ : root@stratix10:~# fio --filename=/dev/nvme0n1 --rw=read --gtod_reduce=1 --blocksize=64k --size=2G --iodepth=2 --group_reporting --name=myjob --ioengine=libaio --numjobs=<no of job>
Result as below.
| Operation |
No of job |
io (amount of IO done) |
aggrb (aggregate bandwidth) |
minb (minimum bandwidth) |
maxb (maximum bandwidth) |
mint (shortest time) |
maxt (longest time) |
|---|
| WRITE |
4 |
8192MB |
1014.9MB/s |
1014.9MB/s |
1014.9MB/s |
8072msec |
8072msec |
| ^ |
8 |
16384MB |
1569.4MB/s |
1569.4MB/s |
1569.4MB/s |
10440msec |
10440msec |
| ^ |
16 |
32768MB |
1723.2MB/s |
1723.2MB/s |
1723.2MB/s |
19016msec |
19016msec |
| ^ |
20 |
40960MB |
1813.2MB/s |
1813.2MB/s |
1813.2MB/s |
22591msec |
22591msec |
| READ |
4 |
8192MB |
1353.0MB/s |
1353.0MB/s |
1353.0MB/s |
6055msec |
6055msec |
| ^ |
8 |
16384MB |
2017.0MB/s |
2017.0MB/s |
2017.0MB/s |
8123msec |
8123msec |
| ^ |
16 |
32768MB |
2270.0MB/s |
2270.0MB/s |
2270.0MB/s |
14438msec |
14438msec |
| ^ |
20 |
40960MB |
2309.0MB/s |
2309.0MB/s |
2309.0MB/s |
17738msec |
17738msec |
Intel SSD NVMe Throughputs
Rebuilding Source Files
The instructions below are optional. They show how to rebuild the software and/or hardware if you want to experiment with the reference design. This reference design is a modified version of the Golden System Reference Design, so please refer to
S10 GSRD - User Manual for more details regarding the build flow. It is highly recommended that you perform all of the relevant compilation steps listed in in the user's manual before continuing. The following steps are only meant to be a minimal list.
Compiling U-Boot FSBL and SSBL
Please refer to
Compiling U-Boot FSBL and SSBL for instructions to compile Stratix 10 SoC U-Boot First Stage Boot Loader (FSBL) and Second Stage Boot Loader (SSBL).
Build Stratix 10 PCIe Root Port and Integrating U-boot FSBL
Additional U-boot Commands Needed for F2H Bridge Coherent Access
U-boot commands below are needed for F2H Bridge coherent access in Cache Coherency Unit (CCU). You may manually enter the commands into U-boot console, save it as an environment variable or execute the commands in u-boot script.
bridge enable; mw ffd24800 60000000; mw F70105a0 0; mw F70105c0 0; mw F70105e0 0; mw F7010600 0; mw F7010620 0; mw F7010640 0; mw 0xf9000210 60782F02;
In prebuilt sdimage.img, these commands are included in U-boot script
u-boot.scr. Please refer to
creating the U-boot script for details to create a U-boot script.
Compiling Linux
If you just want to compile Linux kernel and device tree only and re-use existing Linux Root Filesystem, please run steps below.
- Download this patch to add PCIe root port node into socfpga_stratix10.dtsi in ~/linux-socfpga/arch/arm64/boot/dts/altera/.
- Run commands below to apply the patch and build Linux kernel and Linux device tree.
$ cd ~
$ git clone https://github.com/altera-opensource/linux-socfpga
$ cd linux-socfpga
$ git checkout ACDS19.3_REL_GSRD_PR -b mybranch
$ git apply arm64_dts_add_stratix_10_PCIe_node.patch
$ make defconfig
$ make menuconfig
In kernel configuration, go to "Device Drivers" and input "Y" on "NVM Express block device". Save the changes to .config.
Type "make" to compile the kernel.
$ make
Device Tree Blob file (.dtb) can be found in {linux-socfpga}/arch/arm64/boot/dts/altera.
socfpga_stratix10_socdk.dtb
Existing Linux Root Filesystem can be re-used.
Optionally, you can use Angstrom to generate Linux Kernel, Linux device tree blob and Linux Root Filesystem for the Intel Stratix 10 SoC Development Kit. The steps to do this are documented in the
Compiling Linux for Stratix 10. Executing this step also generates the
gsrd-console-image-stratix10.tar.xz file (root filesystem as compressed tarball that can be used in step
Creating and Updating the SD Card.
Crafting Device Tree Manually for PCIe root port enablement
If you would like to add PCIe root port to your custom dts, PCIe root port bindings below can be added into the dts file.
Please refer to references below for PCIe device tree information.
/{
soc{
s10_hps_bridges: bridge@80000000 {
compatible = "simple-bus";
reg = <0x80000000 0x20200000>,
<0xf9000000 0x00100000>;
reg-names = "axi_h2f", "axi_h2f_lw";
#address-cells = <0x2>;
#size-cells = <0x1>;
ranges = <0x00000000 0x00000000 0x80000000 0x00040000>,
<0x00000000 0x10000000 0x90000000 0x10000000>,
<0x00000000 0x20000000 0xa0000000 0x00200000>,
<0x00000001 0x00010000 0xf9010000 0x00008000>,
<0x00000001 0x00018000 0xf9018000 0x00000080>,
<0x00000001 0x00018080 0xf9018080 0x00000010>;
pcie_0_pcie_s10: pcie@200000000 {
compatible = "altr,pcie-root-port-2.0";
reg = <0x00000000 0x20000000 0x00200000>,
<0x00000000 0x10000000 0x10000000>,
<0x00000001 0x00010000 0x00008000>;
reg-names = "Hip", "Txs", "Cra";
interrupt-parent = <0x5>;
interrupts = <0x0 0x14 0x4>;
interrupt-controller;
#interrupt-cells = <0x1>;
device_type = "pci";
bus-range = <0x0000000 0x000000ff>;
ranges = <0x82000000 0x00000000 0x00000000 0x00000000 0x10000000 0x00000000 0x10000000>;
msi-parent = <&pcie_0_msi_irq>;
#address-cells = <0x3>;
#size-cells = <0x2>;
dma-coherent;
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
interrupt-map = <0x0 0x0 0x0 0x1 &pcie_0_pcie_s10 0x1>,
<0x0 0x0 0x0 0x2 &pcie_0_pcie_s10 0x2>,
<0x0 0x0 0x0 0x3 &pcie_0_pcie_s10 0x3>,
<0x0 0x0 0x0 0x4 &pcie_0_pcie_s10 0x4>;
}; //end pcie@0x010000000 (pcie_0_pcie_s10)
pcie_0_msi_irq: msi@10008080 {
compatible = "altr,msi-1.0";
reg = <0x00000001 0x00018080 0x00000010>,
<0x00000001 0x00018000 0x00000080>;
reg-names = "csr", "vector_slave";
interrupt-parent = <&intc>;
interrupts = <0x0 0x13 0x4>;
msi-controller = <0x1>;
num-vectors = <0x20>;
}; //end msi@0x100008000 (pcie_0_msi_irq)
};
};
};
Creating and Updating SD Card
The picture below presents the layout of the SD card that is used in PCIe root port GSRD.
| Location |
File Name |
Description |
|---|
| FAT32 |
socfpga_stratix10_socdk.dtb |
Linux Device Tree Blob file |
| ^ |
Image |
Linux kernel image file |
| ^ |
u-boot.scr |
U-boot script |
| ^ |
u-boot-dtb.img |
U-boot SSBL |
| ext2 |
various |
Linux root filesystem |
Please refer to
Creating and Updating the SD Card for instructions to create and update SD Card content.
Fixed Known Issues
Intel i210 Gigabit Network Interface Card as end point, during the boot up "Malformed TLP packet" message is shown.
The issue can be resolve by add the below code in the "s10_tlp_read_packet" function in file drivers/pci/controller/pcie-altera.c
for (i = 0; i < 5; i++) {
ctrl = cra_readl(pcie, S10_RP_RXCPL_STATUS);
dw[count-1] = cra_readl(pcie, S10_RP_RXCPL_REG);
printk("status %x data %x\n",ctrl,dw[count-1]);
if (ctrl & RP_RXCPL_EOP) {
return PCIBIOS_SUCCESSFUL;
}
}
dev_warn(dev, "Malformed TLP packet\n");
PCIe root port bindings for i210 NIC in dts file
s10_hps_bridges: bridge@80000000 {
compatible = "simple-bus";
reg = <0x80000000 0x20200000>,
<0xf9000000 0x00100000>;
reg-names = "axi_h2f", "axi_h2f_lw";
#address-cells = <2>;
#size-cells = <1>;
ranges = <0x00000000 0x00000000 0x80000000 0x00040000>,
<0x00000000 0x10000000 0x90100000 0x0ff00000>, /* i210 */
<0x00000000 0x20000000 0xa0000000 0x00200000>,
<0x00000001 0x00010000 0xf9010000 0x00008000>,
<0x00000001 0x00018000 0xf9018000 0x00000080>,
<0x00000001 0x00018080 0xf9018080 0x00000010>;
pcie_0_pcie_s10: pcie@A0000000 {
compatible = "altr,pcie-root-port-2.0";
reg = <0x00000000 0x20000000 0x00200000>,
<0x00000000 0x10000000 0x10000000>,
<0x00000001 0x00010000 0x00008000>;
reg-names = "Hip", "Txs", "Cra";
interrupt-parent = <&intc>;
interrupts = <0 20 4>;
interrupt-controller;
#interrupt-cells = <1>;
device_type = "pci"; /* embeddedsw.dts.params.device_type type STRING */
bus-range = <0x00000000 0x000000ff>;
ranges = <0x82000000 0x00000000 0x00100000 0x00000000 0x10000000 0x00000000 0x0ff00000>; /* i210 */
msi-parent = <&pcie_0_msi_irq>;
#address-cells = <3>;
#size-cells = <2>;
dma-coherent;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie_0_pcie_s10 1>,
<0 0 0 2 &pcie_0_pcie_s10 2>,
<0 0 0 3 &pcie_0_pcie_s10 3>,
<0 0 0 4 &pcie_0_pcie_s10 4>;
}; //end pcie@0x010000000 (pcie_0_pcie_s10)
pcie_0_msi_irq: msi@10008080 {
compatible = "altr,msi-1.0";
reg = <0x00000001 0x00018080 0x00000010>,
<0x00000001 0x00018000 0x00000080>;
reg-names = "csr", "vector_slave";
interrupt-parent = <&intc>;
interrupts = <0 19 4>;
msi-controller = <1>; /* embeddedsw.dts.params.msi-controller type NUMBER */
num-vectors = <32>; /* embeddedsw.dts.params.num-vectors type NUMBER */
}; //end msi@0x100008000 (pcie_0_msi_irq)
};
RocketBoards
You should see the U-Boot bootloader start...
In kernel configuration, go to "Device Drivers" and input "Y" on "NVM Express block device". Save the changes to .config.
Type "make" to compile the kernel.
